An improved PVT-Robust floating inverter dynamic amplifier for noise-shaping SAR ADCs

Abstract

The floating inverter dynamic amplifier (FIDA) is a power-efficient, open-loop, and dynamic amplifier without requiring any output common-mode feedback (CMFB) circuit. It is appropriate for low-power applications. However, its gain is not robust over process, voltage, and temperature (PVT) variations. In this work, a simple, low power, and low noise method is proposed to solve this problem. The proposed method controls the amplification time window of the FIDA to be proportional to its time constant. Based on the FIDA gain formula, this technique stabilizes the gain over PVT changes. The proposed PVT-robust FIDA is designed at the circuit level using 0.18 µm TSMC CMOS technology with Cadence Virtuoso tool. According to the post-layout simulation results of a sample design, the gain of the amplifier is 29.4 with 51.3 µW power consumption from a 1.2 V supply voltage. The maximum gain variation over PVT changes is reduced from 49.6% to 9.8% using the proposed gain calibration technique.