Multithreaded System Research Articles

Drugstore Control System Design and Realization Based on Programmable Logic Controller (PLC)

This paper proposes an intelligent storage and automatic drug delivery system based on PLC. This system can be applied to dispensing work for all type of medicines. Firstly, the essentials of intelligent control system are discussed and then overall scheme of the system design is presented. Secondly, introduction to the software and hardware design of control system, including the selection of PLC and motion control system are described. Lastly, by analysis of E-R diagram, the date is established and communication protocol between systems is customized. This paper also gives the implementations of the multi-threaded system and communication method.

Concurrency-preserving and sound monitoring of multi-threaded component-based systems: theory, algorithms, implementation, and evaluation

Abstract This paper addresses the monitoring of logic-independent linear-time user-provided properties in multi-threaded component-based systems. We consider intrinsically independent components that can be executed concurrently with a centralized coordination for multiparty interactions. In this context, the problem that arises is that a global state of the system is not available to the monitor. A naive solution to this problem would be to plug in a monitor which would force the system to synchronize in order to obtain the sequence of global states at runtime. Such a solution would defeat the whole purpose of having concurrent components. Instead, we reconstruct on-the-fly the global states by accumulating the partial states traversed by the system at runtime. We define transformations of components that preserve their semantics and concurrency and, at the same time, allow to monitor global-state properties. Moreover, we present RVMT-BIP, a prototype tool implementing the transformations for monitoring multi-threaded systems described in the Behavior, Interaction, Priority (BIP) framework, an expressive framework for the formal construction of heterogeneous systems. Our experiments on several multi-threaded BIP systems show that RVMT-BIP induces a cheap runtime overhead.

Optimized wavelet-based texture representation and streaming for GPU texture mapping

Because of the ever increasing resolution of consumer displays, high quality real-time 3D rendering applications require large amounts of 2D texture data, which in turn require large amounts of storage, memory and bandwidth. One of the major advantages of using compressed texture data is the significant decrease in bandwidth requirements, decreasing texture loading times. Additionally, instead of preloading all the potentially required information, texture data can be streamed progressively at run-time, which is a very common scenario in web-based applications, games and large virtual environments. This paper proposes a new texture streaming system, utilizing both pre-computed and run-time scene analysis, camera prediction and wavelet-based texture compression to provide maximal visual quality within bandwidth and real-time constraints. Texture decoding is done on the GPU, saving both on streaming bandwidth and GPU memory. The pre-computed scene analysis system can perform the run-time analysis at virtually no performance cost in multi-threaded systems. The proposed solution can easily be plugged into existing classical texture mapping solutions, as it features drop-in replacement shaders and re-uses existing render facilities. The wavelet-based streaming system results in PSNR improvements of up to 2 dB when compared to a DXT1-based streaming system.

Topology Modeling and Analysis of a Power Grid Network Using a Graph Database

We introduce a new method for storing, modeling, and analyzing power grid data. First, we present an architecture for building the network model for a power grid using the open source graph database Neo4j. Second, we design single- and multi-threading systems for initial energization analysis of the power grid network. We design the shortest path search function and conditional search function based on Neo4j. Finally, we compare the functionality and efficiency of our graph database with a traditional relational database in system initial energization analysis and the shortest path function problems on small to large data sets. The results demonstrate the efficiency and effectiveness of topology modeling and analysis using graph database for a power grid network.

Research of a resource-efficient, real-time and fault-tolerant wireless sensor network system

Memory optimization, energy conservation, real-time scheduling and fault tolerance are the essential research topics in the wireless sensor network (WSN). In this paper, a memory-efficient, energy-efficient, real-time and fault-tolerant WSN system LiveOS is designed and implemented. Compared to the other systems, LiveOS has several typical features. Firstly, the optimized Rate-Monotonic Scheduling (RMS) scheduling algorithm is implemented. By doing this, the memory cost of the multithreaded real-time operating system (RTOS) can be 47.3% optimized if compared to the traditional single-core node. Consequently, the RTOS becomes appropriate to run even on the memory-constrained WSN nodes. Secondly, the new research approach that addresses the WSN challenges by combining both the multi-core hardware technique and the software technique is applied in LiveOS. By means of the multi-core hardware support, the energy cost of LiveOS can be 35% optimized compared to the traditional single-core platform. Moreover, the real-time scheduling performance and the fault-tolerant ability of the WSN nodes can be optimized significantly. Due to the above features, LiveOS becomes the WSN system which has small memory footprint, long lifetime, high real-time scheduling performance and upstanding fault-tolerant ability. The evaluation on the different prototype nodes proves that LiveOS is appropriate to run on the resource-constrained WSN platforms and is competent to execute the outdoor real-time WSN applications.

A virtual tile approach to raster-based calculations of large digital elevation models in a shared-memory system

Grid digital elevation models (DEMs) are commonly used in hydrology to derive information related to topographically driven flow. Advances in technology for creating DEMs have increased their resolution and data size with the result that algorithms for processing them are frequently memory limited. This paper presents a new approach to the management of memory in the parallel solution of hydrologic terrain processing using a user-level virtual memory system for shared-memory multithreaded systems. The method includes tailored virtual memory management of raster-based calculations for datasets that are larger than available memory and a novel order-of-calculations approach to parallel hydrologic terrain analysis applications. The method is illustrated for the pit filling algorithm used first in most hydrologic terrain analysis workflows.

Unveiling the performance‐energy trade‐off in iterative linear system solvers for multithreaded processors

SummaryIn this paper, we analyze the interactions occurring in the triangle performance‐power‐energy for the execution of a pivotal numerical algorithm, the iterative conjugate gradient (CG) method, on a diverse collection of parallel multithreaded architectures. This analysis is especially timely in a decade where the power wall has arisen as a major obstacle to build faster processors. Moreover, the CG method has recently been proposed as a complement to the LINPACK benchmark, as this iterative method is argued to be more archetypical of the performance of today's scientific and engineering applications. To gain insights about the benefits of hands‐on optimizations we include runtime and energy efficiency results for both out‐of‐the‐box usage relying exclusively on compiler optimizations, and implementations manually optimized for target architectures, that range from general‐purpose and digital signal multicore processors to manycore graphics processing units, all representative of current multithreaded systems. Copyright © 2014 John Wiley & Sons, Ltd.

Hybrid Real-time Operating System for Resource-constraint Wireless Sensor Nodes

Wireless sensor network (WSN) has been used in widespread domains, and the real-time response is required by many WSN applications. However, due to the memory resources limitation on the sensor nodes, the current WSN OSs such as TinyOS, Contiki, SOS, mantisOS, etc., are not real-time ones. To achieve the objective of designing a real- time OS with low memory resource consumption, a new WSN OS named HEROS is developed and presented in this paper. For HEROS, it adopts a hybrid scheduling strategy. Both the event-driven and multithreading schedulers are implemented in parallel, and these two schedulers can switch to each other when necessary. By this means, HEROS take advantages of both the event-driven system's low memory resource consumption as well as multithreading system's high real-time performance. Besides these, HEROS uncouples the applications from the underlying systems by using the pre-linked mechanism (PLM). With this mechanism, a user-friendly development environment can be provided to the WSN users. Finally, to evaluate the performance of HEROS, it is compared with some other WSN OSs on the iLive platform (8-bit AVR microcontroller). The final experimental and evaluation results prove that HEROS is a memory resources efficient, real-time supported and user-friendly OS, and can be used on most resource-constrained sensor nodes to support the diverse kinds of WSN applications.

DRDet: Efficiently Making Data Races Deterministic

Strongly deterministic multithreading provides determinism for multithreaded programs even in the presence of data races. A common way to guarantee determinism for data races is to isolate threads by buffering shared memory accesses. Unfortunately, buffering all shared accesses is prohibitively costly. We propose an approach called DRDet to efficiently make data races deterministic. DRDet leverages the insight that, instead of buffering all shared memory accesses, it is sufficient to only buffer memory accesses involving data races. DRDet uses a sound data-race detector to detect all potential data races. These potential data races, along with all accesses which may access the same set of memory objects, are flagged as data-race-involved accesses. Unsurprisingly, the imprecision of static analyses makes a large fraction of shared accesses to be data-race-involved. DRDet employs two optimizations which aim at reducing the number of accesses to be sent to query alias analysis. We implement DRDet on CoreDet, a state-of-the-art deterministic multithreading system. Our empirical evaluation shows that DRDet reduces the overhead of CoreDet by an average of 1.6X, without weakening determinism and scalability.

Integrating Formal UML Designs and HCI Patterns with Spiral SDLC in DroLIGHT Implementation

Abstract: Design engineering of an embedded system is a lot more complex and with greater security risk than a desktop and web application, as it involves several electronic components, micro controllers, external PCB boards and miscellane-ous advanced devices, to be attached, used and properly communicated. Today, embedded systems are widely used for miscellaneous purposes in different fields of life, the goal of this research is to develop a new domain specific real time solution for the fields of Neurobiology and Photobiology. We propose a new embedded and multithreading based system i.e. DroLIGHT, proficient in systematizing a noncommercial special purpose hardware capable of producing lights of dif-ferent brightness and wavelength that can be used to study light-evoked behavior of animals, here especially that of the fruit fly Drosophila melanogaster. The aim of this paper is to discuss initial DroLIGHT implementation, following spiral software development life cycle and integrating a formal unified modelling language to scheme from different perspec-tives e.g. use case, design and implementation views. We present the designed graphical user interface incorporating hu-man computer interaction guidelines, principles and patterns e.g. window per task, direct manipulation, conversational text, ephemeral feedback and step-by-step instructions. We highlight the programming details, available features, hard-ware components and the basic deployment procedure of the DroLIGHT. Moreover the paper discusses a few of the pat-ents relevant to UML Designs and HCI Patterns.

Simulated annealing for improving the solution of the response time variability problem

The response time variability problem (RTVP) is a scheduling problem that has a wide range of real-world applications in mixed-model assembly lines, multi-threaded computer systems, machine maintenance, waste collection and others. The RTVP arises whenever products, clients or jobs need to be sequenced in such a way that the variability in the time between the points at which they receive the necessary resources is minimised. The RTVP has been demonstrated to be NP-hard and heuristic and metaheuristic techniques are needed to solve large, real-life instances. The best results, on average, in the literature for the RTVP were obtained with variable neighbourhood search hybidised with multi-start. Several algorithms based on simulated annealing are proposed to solve the RTVP. An extensive computational experiment is carried out and it is shown that the solution of the RTVP is clearly improved.

Model checking LTL properties over ANSI-C programs with bounded traces

Context-bounded model checking has been used successfully to verify safety properties in multi-threaded systems automatically, even if they are implemented in low-level programming languages such as C. In this paper, we describe and experiment with an approach to extend context-bounded software model checking to safety and liveness properties expressed in linear-time temporal logic (LTL). Our approach checks the actual C program, rather than an extracted abstract model. It converts the LTL formulas into Buchi automata for the corresponding never claims and then further into C monitor threads that are interleaved with the execution of the program under analysis. This combined system is then checked using the ESBMC model checker. We use an extended, four-valued LTL semantics to handle the finite traces that bounded model checking explores; we thus check the combined system several times with different acceptance criteria to derive the correct truth value. In order to mitigate the state space explosion, we use a dedicated scheduler that selects the monitor thread only after updates to global variables occurring in the LTL formula. We demonstrate our approach on the analysis of the sequential firmware of a medical device and a small multi-threaded control application.

Scalable deterministic replay in a parallel full-system emulator

Full-system emulation has been an extremely useful tool in developing and debugging systems software like operating systems and hypervisors. However, current full-system emulators lack the support for deterministic replay, which limits the reproducibility of concurrency bugs that is indispensable for analyzing and debugging the essentially multi-threaded systems software. This paper analyzes the challenges in supporting deterministic replay in parallel full-system emulators and makes a comprehensive study on the sources of non-determinism. Unlike application-level replay systems, our system, called ReEmu, needs to log sources of non-determinism in both the guest software stack and the dynamic binary translator for faithful replay. To provide scalable and efficient record and replay on multicore machines, ReEmu makes several notable refinements to the CREW protocol that replays shared memory systems. First, being aware of the performance bottlenecks in frequent lock operations in the CREW protocol, ReEmu refines the CREW protocol with a seqlock-like design, to avoid serious contention and possible starvation in instrumentation code tracking dependence of racy accesses on a shared memory object. Second, to minimize the required log files, ReEmu only logs minimal local information regarding accesses to a shared memory location, but instead relies on an offline log processing tool to derive precise shared memory dependence for faithful replay. Third, ReEmu adopts an automatic lock clustering mechanism that clusters a set of uncontended memory objects to a bulk to reduce the frequencies of lock operations, which noticeably boost performance. Our prototype ReEmu is based on our open-source COREMU system and supports scalable and efficient record and replay of full-system environments (both x64 and ARM). Performance evaluation shows that ReEmu has very good performance scalability on an Intel multicore machine. It incurs only 68.9% performance overhead on average (ranging from 51.8% to 94.7%) over vanilla COREMU to record five PARSEC benchmarks running on a 16-core emulated system.

Parallel Implementation of 1-D Complex FFT Using Multithreading and Multi-Core Systems

 Abstract—Now-a-days most desktop PCs have multiprocessing technology such as Hyper-Threading (HT), Dual-Core, and Quad-Core processors. Technological developments in microprocessor design have enabled hardware vendors to put multiple cores on a single socket. The main idea is to build software applications that can fully exploit the capabilities of a multi-core system using multithreading approach for faster performance. The aim of this paper is to show the performance enhancement in terms of execution time using multiple threads. This involves executing sequential software application followed by multithreaded software application on Intel based multi-core systems. 1-D complex Fast Fourier Transform (FFT) function has been taken from an open source library, called FFTw, as an example to prove the concept. Finally results show the decrease in execution time with increase in FFT sizes for a multithreaded software application on a multi-core system.

Incremental Dynamic Updates with First-class Contexts.

Highly available software systems occasionally need to be updated while avoiding downtime. Dynamic software updates reduce downtime, but still require the system to reach a quiescent state in which a global update can be performed. This can be difficult for multi-threaded systems. We present a novel approach to dynamic updates using first-class contexts, called Theseus. First-class contexts make global updates unnecessary: existing threads run to termination in an old context, while new threads start in a new, updated context; consistency between contexts is ensured with the help of bidirectional transformations. We show how first-class contexts offer a practical and flexible approach to incremental dynamic updates, with acceptable overhead.

Parallelization of shallow water simulations on current multi-threaded systems

In this work, several parallel implementations of a numerical model of pollutant transport on a shallow water system are presented. These parallel implementations are developed in two phases. First, the sequential code is rewritten to exploit the stream programming model. And second, the streamed code is targeted for current multi-threaded systems, in particular, multi-core CPUs and modern GPUs. The performance is evaluated on a multi-core CPU using OpenMP, and on a GPU using the streaming-oriented programming language Brook+, as well as the standard language for heterogeneous systems, OpenCL.

Protection Structures in Multithreaded Systems

We consider a single-address-space system which implements a form of segmentation with paging within the framework of the multithreaded model of program execution. A salient problem of a system of this type is the definition of the set of mechanisms enforcing memory protection. We present a paradigm for the protection system design that is based on the well-known concepts of protection domains and access rights. The resulting environment guarantees an effective separation of the memory resources of the different processes, whose loosely coupled interactions correspond to explicit actions of information sharing. Within the boundaries of a single multithreaded process, a less-stringent protection requirement is to confine the consequences of a programming error in the thread that originated the error. These results are obtained by taking advantage of techniques of symmetric-key cryptography to represent access privileges in memory at the level of the single pages that form a segment.

On-the-fly extraction of hierarchical object graphs

Abstract Reverse engineering techniques are usually applied to extract concrete architecture models. However, these techniques usually extract models that just reveal static architectures, such as class diagrams. On the other hand, the extraction of dynamic architecture models is particularly useful for an initial understanding on how a system works or to evaluate the impact of possible maintenance tasks. This paper describes an approach to extract hierarchical object graphs (OGs) from running systems. The proposed graphs have the following distinguishing features: (a) they support the summarization of objects in domains, (b) they support the complete spectrum of relations and entities that are common in object-oriented systems, (c) they support multithreading systems, and (d) they include a language to alert about expected (or unexpected) relations between the extracted objects. We also describe the design and implementation of a tool for visualizing the proposed OGs. Finally, we provide two case studies. The first study shows how our approach can contribute to understand the running architecture of two systems (myAppointments and JHotDraw). The second study illustrates how OGs can help to locate defective software components in the JHotDraw system.

Metaheuristic algorithms hybridised with variable neighbourhood search for solving the response time variability problem

The response time variability problem (RTVP) is a scheduling problem with a wide range of real-world applications: mixed-model assembly lines, multi-threaded computer systems, network environments, broadcast of commercial videotapes and machine maintenance, among others. The RTVP arises whenever products, clients or jobs need to be sequenced in such a way that the variability in the time between the points at which they receive the necessary resources is minimised. Since the RTVP is NP-hard, several heuristic and metaheuristic techniques are needed to solve non-small instances. The published metaheuristic procedure that obtained the best solutions, on average, for non-small RTVP instances is an algorithm based on a variant of the variable neighbourhood search (VNS), called Reduced VNS (RVNS). We propose hybridising RVNS with three existing algorithms based on tabu search, multi-start and particle swarm optimisation. The aim is to combine the strengths of the metaheuristics. A computational experiment is carried out and it is shown that, on average, all proposed hybrid methods are able to improve the best published solutions.

Balancing the performance of block multithreaded distributed-memory systems

The performance of modern computer systems is increasingly often limited by long latencies of accesses to the memory subsystems. Instruction-level multithreading is an architectural approach to tolerating such long latencies by switching instruction threads rather than waiting for the completion of memory operations. The paper studies performance limitations in distributed-memory block multithreaded systems and determines conditions for such systems to be balanced. Event-driven simulation of a timed Petri net model of a simple distributed-memory system confirms the derived performance results.