Multithreaded Applications Research Articles

SCOZ: A system‐wide causal profiler for multicore systems

AbstractThe increased complexity of hardware and software makes it difficult to analyze programs with conventional profilers. The causal profiling technique is introduced to solve the problem of conventional profilers. The causal profiling technique finds the bottleneck of the program and shows the effect of optimizing it. COZ, the newest causal profiler, exploits a technique called virtual speedup to perform causal profiling without actually optimizing program codes. However, it can only profile multithreaded applications, and cannot profile multiprogram applications and operating system (OS) kernel codes, thereby limiting the use of causal profiling. This article introduces SCOZ, a system‐wide causal profiler that addresses these limitations. The proposed profiler changes the target of virtual speedup from threads to CPU cores, thereby expanding the profiling coverage to diverse applications as well as OS kernel codes. To verify our profiler, we profiled multithreaded and OS kernel‐intensive applications. For multithread applications, our profiler shows identical results to what COZ provides. For the OS kernel‐intensive applications, our profiler identifies identical bottlenecks that previous OS scalability studies have pinpointed. Finally, we verified the profiling capability of the proposed profiler by profiling and optimizing multiprocess applications in the NAS parallel benchmark suite.

Critical pipeline of the acyclic wave processor

This paper is devoted to studying the performance of an acyclic wave processor consisting of heterogeneous processor elements having various delays. Data channels have sufficiently large buffers. The main result is the proof of the conjecture that for an arbitrary amount of input data, an acyclic wave processor contains a pipeline whose operating time is equal to the data processing time using the entire wave processor. This pipeline is called critical. For partially testing the conjecture, a multi-threaded application simulating the work of a two-dimensional pipeline has been developed. Earlier, the author proposed an algorithm for calculating the input processing time, the complexity of which depends not only on the number of stages but also on the amount of data. The proven conjecture eliminates this drawback, it allows building algorithms for calculating data processing time, the complexity of which does not depend on the amount of data. In particular, for any class of acyclic wave processors that have some algorithm of polynomial complexity for listing maximum pipelines, it is easy to construct a polynomial algorithm for calculating the data processing time for an arbitrary volume.

Real-time plasma position reflectometry system development and integration on COMPASS tokamak

O-mode frequency-modulated continuous wave (FMCW) reflectometry provides an alternative to magnetic measurements in the determination of the plasma separatrix position for plasma position control. This type of measurement proves to be particularly attractive for the control of future fusion reactors where the harsh radiation environment may damage magnetic probes or induce non-compensable measurement drifts. Plasma position reflectometry (PPR), first demonstrated in ASDEX-Upgrade, is a control technique that is increasingly important to validate in diversified experimental devices and relevant plasma regimes. The COMPASS tokamak provides suitable conditions for such advanced demonstrations and regular PPR operation and development, thanks to its O-mode reflectometer and Multi-Threaded Application Real-Time executor (MARTe) based real-time control system. Herein we present the integration of a PPR system on COMPASS, both at hardware and software levels. Reflectometry swept measurements require signals to be acquired in bursts of data and streamed to the corresponding MARTe-PPR node through PCIe® fibre-optic links. The data transferred in real-time is used to reconstruct the radial density profiles from which the outer separatrix position is estimated. This estimate is then delivered to the central MARTe controller node via a dedicated Xilinx® Aurora® link at a rate matching COMPASS's 500 μs slow control cycle. The implemented system systematically met the required latency specifications, being able to deliver an estimation of the plasma radial position capable of successfully replacing the corresponding magnetic measurements in the plasma position feedback control loops.

PkMin: Peak Power Minimization for Multi-Threaded Many-Core Applications

Multiple multi-threaded tasks constitute a modern many-core application. An accompanying generic Directed Acyclic Graph (DAG) represents the execution precedence relationship between the tasks. The application comes with a hard deadline and high peak power consumption. Parallel execution of multiple tasks on multiple cores results in a quicker execution, but higher peak power. Peak power single-handedly determines the involved cooling costs in many-cores, while its violations could induce performance-crippling execution uncertainties. Less task parallelization, on the other hand, results in lower peak power, but a more prolonged deadline violating execution. The problem of peak power minimization in many-cores is to determine task-to-core mapping configuration in the spatio-temporal domain that minimizes the peak power consumption of an application, but ensures application still meets the deadline. All previous works on peak power minimization for many-core applications (with or without DAG) assume only single-threaded tasks. We are the first to propose a framework, called PkMin, which minimizes the peak power of many-core applications with DAG that have multi-threaded tasks. PkMin leverages the inherent convexity in the execution characteristics of multi-threaded tasks to find a configuration that satisfies the deadline, as well as minimizes peak power. Evaluation on hundreds of applications shows PkMin on average results in 49.2% lower peak power than a similar state-of-the-art framework.

Cooperative scheduling of multi‐core and cloud resources: fine‐grained offloading strategy for multithreaded applications

Nowadays, advanced smart mobile devices equipped with multi-core central processing units for handling multithreaded (MT) applications. However, existing research mainly uses single-thread (ST) computing to deal with applications, which limits the performance of mobile computing. To make full use of multi-core resources, this study proposes a fine-grained MT offloading strategy to solve the offloading problem of MT application. The strategy jointly schedules cloud computing resources, as well as local multi-core computing and communication resources. Precisely, the authors first formulate the minimum energy consumption problem for ST offloading. Then, they prove that the problem is convex and solve it by standard convex optimisation technique. Thirdly, they extend the optimisation goals from ST applications to MT applications, and design calculation rules for MT applications to reduce computing costs. Finally, based on these calculation rules and the optimal solution for ST offloading, they develop a MT offloading strategy to solve the computation offloading problem of MT applications. Simulation results show that the proposed fine-grained MT offloading strategy effectively reduces the minimum delay requirement of mobile computing.

Improving the performance of fragments of computer code with high time costs based on parallel programming technologies

This article describes the process of converting the program from single-threaded to multithreaded mode. The influence of the number of threads of execution on the total execution time of the code. The problem of spending much time to run programs solved by incremental parallelization when the code is designed for sequential execution, are added to the parallelizing directives. Are similar libraries for working with threads in other programming languages and the advantages of OpenMP over other libraries. Considered a model of parallelizing OpenMP directives, which is time-consuming to run the snippet in multi-threaded mode. The article also presents example code implemented using the C++ language, which built the parallelizing directives of OpenMP. In this model, the estimated execution time of a code snippet of a program with different number of threads. The study showed that with increasing the number of threads the run time is significantly reduced on the average in 1,5–2 times. This happens until the moment when the number of threads will be equal to the number of processor cores. If the number of threads becomes greater than the number of processor cores, the execution time of the program remains virtually unchanged. Are the OpenMP library allows to significantly shorten the program, which can be critical for works of real-time systems, to reduce the time of creating multithreaded applications is simple inserts directives of the library, to reduce the number of errors made by the programmer in the course of working with multi-threaded applications.

A Scalable Virtual memory system based on decentralization for many-cores

Abstract Traditional centralized virtual memory system design encounters severe scalability problems, which impede the multithreaded applications’ performance increment on many-core systems. In this paper, we propose a decentralized system model to scale the VM systems for many-cores. Our model improves system parallelism by avoiding resource sharing and minimizing state coordination. By applying the model, we build a novel scalable virtual memory system called MedusaVM+ . MedusaVM+ presents a decentralized system architecture, which avoids resource conflicts or cache line contention among processors or threads. Furthermore, MedusaVM+ provides a scalable address space by incorporating decentralized VM space management and a hybrid page table design. Critical system services and internal system operations, such as TLB coherence, are also fully optimized to maximize the system parallelism. Our prototype system is implemented based on the Linux kernel 4.4.0 and glibc 2.23. Experimental results evaluated on a 72-core machine demonstrate that MedusaVM+ scales much better than the state-of-the-art systems and decreases the memory consumption by up to 27 × compared with current approaches. For microbenchmark experiments, MedusaVM+ achieves nearly linear performance speedup. When evaluated with multithreaded applications, MedusaVM+ also outperforms other systems by up to a factor of 4.5 × .

Investigating the efficiency of multithreading application programming interfaces for parallel packet classification in wireless sensor networks

This paper investigates the most appropriate application programming interface API that best accelerates the flow-based applications on the wireless sensor networks WSNs . Each WSN include many sensor nodes which have limited resources. These sensor nodes are connected together using base stations. The base stations are commonly network systems with conventional processors which are responsible for handling a large amount of communicated data in flows of network packets. For this purpose, classification of the communicated packets is considered the primary process in such systems. With the advent of high-performance multicore processors, developers in the network industry have considered these processors as a striking choice for implementing a wide range of flow-based wireless sensor networking applications. The main challenge in this field is choosing and exploiting an API which best allows multithreading; i.e. one which maximally hides the latency of performing complex operations by threads and increases the overall efficiency of the cores. This paper assesses the efficiency of Thread, Open Multiprocessing, and Threading Building Blocks TBB libraries in multithread implementation of set-pruning and grid-of-tries packet classification algorithms on dual-core and quad-core processors. In all cases, the speed and throughput of all parallel versions of the classification algorithms are much more than the corresponding serial versions. Moreover, for parallel classification of a sufficiently large number of packets by both classification algorithms, TBB library results in higher throughput and performance than the other libraries due to its automatic scheduling and internal task stealing mechanism.

Testing of multithreaded applications with locks on non-atomic variables

Subject of Research. The paper presents the study of fuzz testing algorithm for “data race” type fault finding in multithreaded software. The algorithm is implemented in the Google TSan tool. The disadvantage of the studied algorithm is the inability to test software products which use non-atomic variables. At this, the use of such tool is excluded for testing of modern applications that implement joint access of program streams to data. We propose a new algorithm for fuzz testing of multithreaded applications and a method for its implementation in the fuzz testing module of the Google TSan tools. Method. Various combinations of the execution of program streams are the input data in the process of fuzz testing of multithreaded applications. The proposed method of fuzz testing for multithreaded software applications assumes that errors in multithreaded applications manifest themselves only at the threads switching points, also called synchronization points. The thread scheduler is implemented as simply as possible. Each thread is assigned with a status marker tracking its activity during the program running. A thread can be in an unknown state (until the first synchronization point), in a state of execution, in a state of waiting in a queue for execution, as well as in a state where the thread has spent its execution quantum but has not reached the synchronization point. Such thread state is automatically changed to the state of waiting at the synchronization point. Thread control is carried out using a separate program thread that monitors the status of all threads and exposes the corresponding marker to the threads that have spent the execution quantum. The error search mechanism is implemented in the software product at the compilation stage by specifying the appropriate options. Main Results. A new fuzz testing module has been integrated in the Google TSan tool, which finds “data race” errors in any multithreaded applications, both with synchronization of access to shared data and with shared access to data. Practical Relevance. Verification of multithreaded software with shared access to data, in particular case of applying non-atomic variables, is especially relevant for the heavily loaded scalable software systems.

An efficient multi-threaded memory allocator for PDES applications

Parallel Discrete Event Simulation (PDES) aims at providing high performance solutions for simulation with large and complex models. Like traditional multi-threaded applications, PDES applications are also confronted with large overhead produced by memory allocation. Especially, complex models and frequent inter-thread communications in PDES applications will lead to large amounts of memory allocation and deallocation requests. Inter-thread communications are implemented by sending and receiving events based on shared memory. Hence, an efficient memory allocator has great impact on the performance of such applications. Current well-known allocators are dedicated to be scalable and lock-free. However, they ignore the difference between thread local and shared memory and manage them in the same way, which cannot make good use of their own characteristics. To solve this problem, this paper proposes a high efficient multi-threaded memory allocator named HMalloc, which innovatively separates thread local memory from shared memory. Thus, local memory allocation and deallocation will not lead to false sharing and lock contention. Moreover, coalescence free is applied to free local memory blocks. Furthermore, a flag-based shared memory management method is proposed to achieve lock-free shared memory allocation and deallocation. Experimental results show that HMalloc can achieve significant performance improvement in both traditional memory allocation benchmarks and typical PDES benchmarks when compared with existing well-known memory allocators.

Deadlocks Detection in Multithreaded Applications Based on Source Code Analysis

This paper extends multithreaded application source code model and shows how to using it to detect deadlocks in C language applications. Four known deadlock scenarios from literature can be detected using our model. For every scenario we created theorems and proofs whose fulfillment guarantees the occurrence of deadlocks in multithreaded applications. Paper also contains comparison of multithreaded application source code model and Petri nets and describe advantages and disadvantages both of them.

Pursuing Extreme Power Efficiency With PPCC Guided NoC DVFS

In sharp contrast to conventional performance indicative based Network-on-Chip (NoC) DVFS, where the direct relation between application performance and NoC power consumption is missing, we exploit the concept of Performance-Power Characteristic Curve (PPCC) newly proposed in the literature to approach maximum NoC power efficiency. PPCC, which defines the direct relation between application performance and NoC power consumption, consists of three distinct regions: an inertial region due to power under-provisioning, a linear region for proportional performance gain, and a saturation region due to power over-provisioning. With PPCC as a guidance, we propose $\Delta$ Δ -DVFS, which employs a “profile-then-select” strategy to step-by-step approach maximum NoC power efficiency. $\Delta$ Δ -DVFS is built on two observations. First, in multi-threaded applications, maximum NoC power efficiency is achieved at the boundary between the linear region and the saturation region on the PPCC. Second, PPCC stabilizes when threads repeat workloads of the same loop. This is intuitively meaningful because loop repetition stresses NoC with similar workload. Based on the observations, $\Delta$ Δ -DVFS uses the first several loop iterations for PPCC profiling. After the profiling is done, $\Delta$ Δ -DVFS selects and applies the optimal V/F that achieves maximum NoC power efficiency to the remaining loop iterations. To accurately and timely follow PPCC when threads proceed to different loops, $\Delta$ Δ -DVFS utilizes an H-tree loop monitor to detect loop change among distributive threads.

An efficient cache flat storage organization for multithreaded workloads for low power processors

The cache hierarchy of current multicores typically consists of three levels, ranging from the faster and smaller L1 level to the slower and larger L3 level. This approach has been demonstrated to be effective in high performance processors, since it reduces the average memory access time. However, when implemented in devices where energy efficiency becomes critical, like low power or embedded processors, conventional cache hierarchies may present some concerns. These concerns, which incur a waste of area and energy, are multiple cache lookups, block replication, block migration and private cache space overprovisioning. To deal with these issues, in this work we propose FOS-Mt, a new cache organization aimed at addressing energy savings in current multicores for multithreaded applications. FOS-Mt’s cache hierarchy consists of only two levels: the L1 cache level located in the core pipeline, and a single and flattened second level which conforms an aggregated cache space which is accessible by all the execution cores. This level is sliced into multiple small buffers, which are dynamically assigned to any of the running thread when they are expected to improve the system performance. Those buffers that are not allocated to any core are powered off to save energy. Experimental results show that FOS-Mt significantly reduces both static and dynamic energy consumption over other conventional cache organizations like NUCA or shared caches with the same storage capacity. Compared to the widely known cache decay approach, FOS-Mt achieves an improvement in the energy delay product by 19.3% on average. Moreover, despite the fact that FOS-Mt is an energy-aware architecture, performance is scarcely affected, since it is kept similar to that one achieved by conventional and cache decay approaches.

ALEXIA

Illegal use of memory pointers is a serious security vulnerability. A large number of malwares exploit the spatial and temporal nature of these vulnerabilities to subvert execution or glean sensitive data from an application. Recent countermeasures attach metadata to memory pointers, which define the pointer’s capabilities. The metadata is used by the hardware to validate pointer-based memory accesses. However, recent works have considerable overheads. Further, the pointer validation is decoupled from the actual memory access. We show that this could open up vulnerabilities in multithreaded applications and introduce new vulnerabilities due to speculation in out-of-order processors. In this article, we demonstrate that the overheads can be reduced considerably by efficient metadata management. We show that the hardware can be designed in a manner that would remain safe in multithreaded applications and immune to speculative vulnerabilities. We achieve these by ensuring that the pointer validations and the corresponding memory access is always done atomically and in order. To evaluate our scheme, which we call ALEXIA, we enhance an OpenRISC processor to perform the memory validation at runtime and also add compiler support. ALEXIA is the first hardware countermeasure scheme for memory protection that provides such an end-to-end solution. We evaluate the processor on an Altera FPGA and show that the runtime overhead, on average, is 14%, with negligible impact on the processor’s size and clock frequency. There is also a negligible impact on the program’s code and data sizes.

Real-time multi-threaded reflectometry density profile reconstructions on COMPASS Tokamak

In COMPASS tokamak, the ordinary mode (O-mode) microwave reflectometry diagnostic has been equipped with an upgraded acquisition system and dedicated computational node running the Multi-Threaded Application Real-Time executor (MARTe). This upgrade aims at the deployment of a real-time (RT) plasma position reflectometry (PPR) diagnostic system for future application in closed-loop plasma position control experiments. The system is synchronized with COMPASS MARTe main controller slow cycle, running at 500 μs, and allows a maximum measurement delivery latency of 450 μs. The RT signal processing algorithms, used to reconstruct the O-mode density profiles are the most time consuming step in the control cycle. This is due to the computation of a large number of Fast Fourier Transforms (FFT) over long data arrays, produced for each reflectometry profile measurement. MARTe is a software control framework that allows the integration of external C/C++ libraries and code such as the FFTW3 C library, a highly optimized and performant implementation of the FFT algorithm into the real-time designs. The framework also provides a set of tools to handle the execution of parallel threads, which can be used to expedite the execution of computationally demanding signal processing algorithms. Herein, we present the processing architecture implemented for the multi-threaded reflectometry density profile reconstruction on MARTe framework, using the FTTW3 library. Consistent systematic results have shown that the implemented solution satisfies COMPASS slow control cycle maximum data latency requirement. Moreover, the obtained reduced latency opens the possibility to either increase the number of processed measurements, leading to a more robust plasma position estimate or even to provide multiple position measurements during each control cycle.

Influence of detailed mechanisms of chemical kinetics on propagation and stability of detonation wave in H2/O2 mixture

In the present paper, detonation in a stoichiometric oxygen-hydrogen mixture is simulated numerically using 4 detailed chemical mechanisms. The effect of chemical kinetics models on the stability of 1D detonation wave and 2D detonation wave propagating in a plane channel is investigated. The number of detonation cells formed in a channel of a given width at different degrees of overdrive is determined. Simulations are performed using a previously developed computational program based on high-order shock-capturing TVD schemes and a finite-rate chemistry solver. The program is implemented in C++ using the CUDA parallel computing platform for running on graphic processor devices (GPU), the open OpenMP standard for multi-threaded applications on multiprocessor systems with shared memory and the MPI protocol for data exchange between processors.

Alleria

Application analysis and simulation tools are used extensively by embedded system designers to improve existing optimization techniques or develop new ones. We propose the Alleria framework to make it easier for designers to comprehensively collect critical information such as virtual and physical memory addresses, accessed values, and thread schedules about one or more target applications. Such profilers often incur substantial performance overheads that are orders of magnitude larger than native execution time. We discuss how that overhead can be significantly reduced using a novel profiling mechanism called adaptive profiling. We develop a heuristic-based adaptive profiling mechanism and evaluate its performance using single-threaded and multi-threaded applications. The proposed technique can improve profiling throughput by up to 145% and by 37% on an average, enabling Alleria to be used to comprehensively profile applications with a throughput of over 3 million instructions per second.

Will My Program Break on This Faulty Processor?

Formal verification is approaching a point where it will be reliably applicable to embedded software. Even though formal verification can efficiently analyze multi-threaded applications, multi-core processors are often considered too dangerous to use in critical systems, despite the many benefits they can offer. One reason is the advanced memory consistency model of such CPUs. Nowadays, most software verifiers assume strict sequential consistency, which is also the naïve view of programmers. Modern multi-core processors, however, rarely guarantee this assumption by default. In addition, complex processor architectures may easily contain design faults. Thanks to the recent advances in hardware verification, these faults are increasingly visible and can be detected even in existing processors, giving an opportunity to compensate for the problem in software. In this paper, we propose a generic approach to consider inconsistent behavior of the hardware in the analysis of software. Our approach is based on formal methods and can be used to detect the activation of existing hardware faults on the application level and facilitate their mitigation in software. The approach relies heavily on recent results of model checking and hardware verification and offers new, integrative research directions. We propose a partial solution based on existing model checking tools to demonstrate feasibility and evaluate their performance in this context.

Convoider: A Concurrency Bug Avoider Based on Transparent Software Transactional Memory

Software transactional memory is an effective mechanism to avoid concurrency bugs in multi-threaded programs. However, two problems hinder the adoption of traditional such systems in wild world: high human cost for equipping programs with transaction functionality and low compatibility with I/O calls and conditional variables. This paper presents Convoider to try to solve these problems. By intercepting inter-thread operations and designating code among them as transactions in each thread, Convoider automatically transactionalizes target programs without any source code modification and recompiling. By saving/restoring stack frames and CPU registers on beginning/aborting a transaction, Convoider makes execution flow revocable. By turning threads into processes, leveraging virtual memory protection and customizing memory allocation/deallocation, Convoider makes memory manipulations revocable. By maintaining virtual file systems and redirecting I/O operations onto them, Convoider makes I/O effects revocable. By converting lock/unlock operations to no-ops, customizing signal/wait operations on condition variables and committing memory changes transactionally, Convoider makes deadlocks, data races and atomicity violations impossible. Experimental results show that Convoider succeeds in transparently transactionalizing twelve real-world applications and perfectly avoid 94% of thirty-one concurrency bugs used in our experiments. This study can help efficiently transactionalize legacy multi-threaded applications and effectively improve the runtime reliability of them.

AdaMD: Adaptive Mapping and DVFS for Energy-Efficient Heterogeneous Multicores

Modern heterogeneous multicore systems, containing various types of cores, are increasingly dealing with concurrent execution of dynamic application workloads. Moreover, the performance constraints of each application vary, and applications enter/exit the system at any time. Existing approaches are not efficient in such dynamic scenarios, especially if applications are unknown, as they require extensive offline application analysis and do not consider the runtime execution scenarios (application arrival/completion, and workload and performance variations) for runtime management. To address this, we present AdaMD, an adaptive mapping and dynamic voltage and frequency scaling (DVFS) approach for improving energy consumption and performance. The key feature of the proposed approach is the elimination of dependency on offline profiled results while making runtime decisions. This is achieved through a performance prediction model having a maximum error of 7.9% lower than the previously reported model and a mapping approach that allocates processing cores to applications while respecting performance constraints. Furthermore, AdaMD adapts to runtime execution scenarios efficiently by monitoring the application status, and performance/workload variations to adjust the previous DVFS settings and thread-to-core mappings. The proposed approach is experimentally validated on the Odroid-XU3, with various combinations of diverse multithreaded applications from PARSEC and SPLASH benchmarks. Results show energy savings of up to 28% compared to the recently proposed approach while meeting performance constraints.