Critical pipeline of the acyclic wave processor

Abstract

This paper is devoted to studying the performance of an acyclic wave processor consisting of heterogeneous processor elements having various delays. Data channels have sufficiently large buffers. The main result is the proof of the conjecture that for an arbitrary amount of input data, an acyclic wave processor contains a pipeline whose operating time is equal to the data processing time using the entire wave processor. This pipeline is called critical. For partially testing the conjecture, a multi-threaded application simulating the work of a two-dimensional pipeline has been developed. Earlier, the author proposed an algorithm for calculating the input processing time, the complexity of which depends not only on the number of stages but also on the amount of data. The proven conjecture eliminates this drawback, it allows building algorithms for calculating data processing time, the complexity of which does not depend on the amount of data. In particular, for any class of acyclic wave processors that have some algorithm of polynomial complexity for listing maximum pipelines, it is easy to construct a polynomial algorithm for calculating the data processing time for an arbitrary volume.