Multistage Interconnection Networks Research Articles

Mapping of Deep Neural Network Accelerators on Wireless Multistage Interconnection NoCs

In the last few decades, the concept of Wireless Network-on-chip (WiNoC) has emerged as a promising alternative for Multiprocessor Systems on Chip (MPSOC) to achieve reliable and scalable communication. Worth recalling in this regard is that our research team has already designed, verified and evaluated Multistage Interconnection Networks (MIN) in this field. With respect to the present work, we consider proceeding with further exploring our thoughts on this research area. Firstly, we propose the design and performance evaluation of a hybrid (wireless/wired) MIN, analysing how this augmented network can potentially improve not only the average delay, but also energy consumption. Secondly, we continue with examining the implementation of our advanced DELTA-based MIN architecture on Deep Neural Network (DNN) accelerators, while accounting for its potential regularity and scalability in simultaneously maintaining an effective power efficiency and lower latency throughout the DNN operating process. In this context, several metrics have been evaluated in regard to three DNN application cases through implementation of their main respective modules.

MPI reduction and broadcast algorithms for computer clusters with multistage interconnection networks

Algorithms for MPI Allreduce, Bcast and Reduce collective operations have been developed. They are based on the dynamic construction of process groups at all levels of the memory hierarchy within the computing node and levels of the multistage interconnection network. The description of the network topology is loaded from an external file. Аlgorithms are implemented on the basis of the Open MPI library in an isolated collective component. Experiments on a cluster with a two-tier InfiniBand EDR network have shown the effectiveness of the algorithms for messages up to 16KB.

Reliable Gamma-Interconnection Network for Data Analysis in Sensor Networks: Design and Performance Evaluation

In today’s era of high speed 5G internet all electronic sensor networks are connected through IoT. Bank transactions are digitized, people can access any data through their mobile phones, organizations and companies handle their projects through online meetings etc. Military and medical surveillance, navy navigation, weapon controlling, weather forecasting etc. involve big data analysis collected from sensors, that too at a very high speed with reliable results. This requires large number of parallel processors connected with huge Bank of memory modules to store big data. Reliable interconnection network is needed to connect these large number of parallel processors and memory modules efficiently hence Multistage Interconnection Networks (MINs) come into play, as they provide highly reliable communication for big data transfer between processors and memory modules whenever required. In this manuscript a new network named Reliable Gamma-interconnection Network (RGN) is introduced which possesses multiple paths between processors and memory modules with two totally disjoint path availability. It provides high reliability and minimum path distance between source node to destination node than other gamma networks known, with the minimum hardware complexity. Reliability estimation and evaluation of RGN has been presented in this paper and comparison of results achieved with other gamma networks has been done for validation purpose.

Omega multistage interconnection network manages double-pattern traffic with a regulator and high-speed forwarding method

This study proposes a flexible and effective solution for developing high-performance multistage interconnection networks to maximize the performance of parallel computer systems, cloud computing infrastructure, grids, etc. An omega-type multistage interconnection network, consisting of regulated switchboxes, is used as a testbed to handle flexible two-class load patterns. The wormhole routing method and a special forwarding technique controlled by a global regulator are adopted to alleviate internal ‘tree saturation’ caused by periodic hotspot traffic combined with uniform traffic. Simulation experiments prove that this concept reduces packet latency, and an additional layer inserted in the final stage further improves the network’s architecture.

Fault Tolerant Gamma-Minus Network

In large-scale supercomputers thousands of processors are connected together to their respective memory modules which are controlled by several control units connected in parallel. Large data streams have to be communicated between these processors and memories through interconnection networks. Multistage interconnection network (MIN) is an efficient way to provide these communications at a very reasonable cost. For such large systems MIN employed should be highly reliable and fast to meet the desired specifications of these high speed switch fabrics. In this paper two new architectures of MIN are proposed which are named as fault-tolerant Gamma-Minus (FTGM-1 & FTGM-2) networks. These proposed architectures are multipath MIN with totally disjoint paths and are highly reliable and fault tolerant. The routing algorithm proposed for these structures is simple distance tag routing with non-backtracking which overcomes rerouting overheads and hence improve communication delays. The proposed MIN ensures multiple fault tolerance at each stage including input and output stage with minimal horizontal distance between source node to destination node. For validating the results, a comparison has been presented between existing MINs with these proposed designs. The proposed MINs outperform the existing MIN in terms of reliability, fault tolerance and up to some extent cost as well.

A machine learning assisted optical multistage interconnection network: Performance analysis and hardware demonstration

AbstractIntegration of the machine learning (ML) technique in all‐optical networks can enhance the effectiveness of resource utilization, quality of service assurances, and scalability in optical networks. All‐optical multistage interconnection networks (MINs) are implicitly designed to withstand the increasing high‐volume traffic demands at data centers. However, the contention resolution mechanism in MINs becomes a bottleneck in handling such data traffic. In this paper, a select list of ML algorithms replaces the traditional electronic signal processing methods used to resolve contention in MIN. The suitability of these algorithms in improving the performance of the entire network is assessed in terms of injection rate, average latency, and latency distribution. Our findings showed that the ML module is recommended for improving the performance of the network. The improved performance and traffic grooming capabilities of the module are also validated by using a hardware testbed.

Design and Reliability Evaluation of Switching Element for Improving the QoS of Multistage Interconnection Network

Reliable and cost effective multistage interconnection networks (MINs) are the backbone of efficient distributed computing in supercomputer systems. In this paper new 3×3, 4×2, and 4×4 switching element (SE) structures are introduced which can be employed in various existing MINs to provide enhanced reliability at much reduced cost. The reliability function of proposed as well as the existing SEs have been formulated on basis of which their reliability values have been computed. The computed reliability values of all SEs (existing and proposed ones) have been compared and analyzed. The achieved results clearly depicts that the proposed SEs possess higher reliability and can replace the existing SEs of similar size without changing the existing design of MIN to improve reliability.

Modified Gamma Network: Design and Reliability Evaluation

Background: VLSI technology advancements have resulted the requirements of high computational power, which can be achieved by implementing multiple processors in parallel. These multiple processors have to communicate with their memory modules by using Interconnection Networks (IN). Multistage Interconnection Networks (MIN) are used as IN, as they provide efficient computing with low cost. Objective: The objective of the study is to introduce new reliable Gamma MIN named as a Modified Gamma Interconnection Network (MGIN), which provide reliability and fault-tolerance with less number of stages of Switching element only. Methods: Switching Element (SE) of bigger size i.e. 2×3/3×2 has been employed at input/output stages inspite of 1×3/3×1 sized SE at input/output stages with reduction in one intermidiate stage. Fault tolerance has been introduced in the form of disjoint paths formed between each sourcedestnation node pair. Hence reliability has been improved. Results: Terminal, Broadcast and Network Reliability has been evaluated by using Reliability Block Diagrams for each source-destination node pair. The results have been shown, which depicts the higher reliability values for newly proposed network. The cost analysis shows that new MGIN is a cheaper network than other Gamma variants. Conclusion: MGIN has better reliability and Fault-tolerance than priviously proposed Gamma MIN.

Investigating Multilayer Omega-Type Networks Operating with the Cut-Through Technique under Uniform or Hotspot Traffic Conditions

The continuous increase in the complexity of data networks has motivated the development of more effective Multistage Interconnection Networks (MINs) as important factors in providing higher data transfer rates in various switching divisions. In this paper, semi-layer omega-class networks operating with a cut-through forwarding technique are chosen as test-bed subjects for detailed evaluation, and this network architecture is modelled, inspected, and simulated. The results are examined for relevant singlelayer omega networks operating with cut-through or ‘store and forward’ forwarding techniques. Two series of experiments are carried out: one concerns the case of uniform traffic, while the other is related to hotspot traffic. The results quantify the way in which this network outperforms the corresponding singlelayer network architectures for the same network size and buffer size. Furthermore, the effects of the dimensions of the switch elements and their corresponding reliability on the overall interconnection system are investigated, and the complexity and the relevant cost are examined. The data yielded by this investigation can be valuable to MIN engineers and can allow them to achieve more productive networks with lower overall implementation costs.

A novel design layout of three disjoint paths multistage interconnection network & its reliability analysis

Purpose The purpose of this paper is to design a efficient layout of Multistage interconnection network which has cost effective solution with high reliability and fault-tolerence capability. For parallel computation, various multistage interconnection networks (MINs) have been discussed hitherto in the literature, however, these networks always required further improvement in reliability and fault-tolerance capability. The fault-tolerance capability of the network can be achieved by increasing the number of disjoint paths as a result the reliability of the interconnection networks is also improved. Design/methodology/approach This proposed design is a modification of gamma interconnection network (GIN) and three disjoint path gamma interconnection network (3-DGIN). It has a total seven number of paths for all tag values which is uniform out of these seven paths, three paths are disjoint paths which increase the fault tolerance capability by two faults. Due to the presence of more paths than the GIN and 3-DGIN, this proposed design is more reliable. Findings In this study, a new design layout of a MIN has been proposed which provides three disjoint paths and uniformity in terms of an equal number of paths for all source-destination (S-D) pairs. The new layout contains fewer nodes as compared to GIN and 3-DGIN. This design provides a symmetrical structure, low cost, better terminal reliability and provides an equal number of paths for all tag values (|S-D|) when compared with existing MINs of this class. Originality/value A new design layout of MINs has been purposed and its two terminal reliability is calculated with the help of the reliability block diagram technique.

A Primer on Design Aspects and Recent Advances in Shuffle Exchange Multistage Interconnection Networks

Interconnection networks provide an effective means by which components of a system such as processors and memory modules communicate to provide reliable connectivity. This facilitates the realization of a highly efficient network design suitable for computational-intensive applications. Particularly, the use of multistage interconnection networks has unique advantages as the addition of extra stages helps to improve the network performance. However, this comes with challenges and trade-offs, which motivates researchers to explore various design options and architectural models to improve on its performance. A particular class of these networks is shuffle exchange network (SEN) which involves a symmetric N-input and N-output architecture built in stages of N/2 switching elements each. This paper presents recent advances in multistage interconnection networks with emphasis on SENs while discussing pertinent issues related to its design aspects, and taking lessons from the past and current literature. To achieve this objective, applications, motivating factors, architectures, shuffle exchange networks, and some of the performance evaluation techniques as well as their merits and demerits are discussed. Then, to capture the latest research trends in this area not covered in contemporary literature, this paper reviews very recent advancements in shuffle exchange multistage interconnection networks within the last few years and provides design guidelines as well as recommendations for future consideration.

Introducing an optimal QCA crossbar switch for baseline network

Crossbar switch is the basic component in multi-stage interconnection networks. Therefore, this study was conducted to investigate performance of a crossbar switch with two multiplexers. The presented crossbar switch was simulated using quantum-dot cellular automata (QCA) technology and QCA Designer software, and was studied and optimized in terms of cell number, occupied area, number of clocks, and energy consumption. Using the provided crossbar switch, the baseline network was designed to be optimal in terms of cell number and occupied area. Also, the number of input states was investigated and simulated to verify accuracy of the baseline network. The proposed crossbar switch uses 62 QCA cells and the occupied area by the switch is equal to 0.06?m2 and its latency equals 4 clock zones, which is more efficient than the other designs. In this paper, using the presented crossbar switch, the baseline network was designed with 1713 cells, and occupied area of 2.89?m2.

SEGIN-Minus: A New Approach to Design Reliable and Fault-Tolerant MIN

Background:VLSI technology advancements have resulted the requirements of high computational power, which can be achieved by implementing multiple processors in parallel. These multiple processors have to communicate with their memory modules by using Interconnection Networks (IN). Multistage Interconnection Networks (MIN) are used as IN, as they provide efficient computing with low cost.Objective:the objective of the study is to introduce new reliable MIN named as a (Shuffle Exchange Gamma Interconnection Network Minus) SEGIN-Minus, which provide reliability and faulttolerance with less number of stages.Methods:MUX at input terminal and DEMUX at output terminal of SEGIN has been employed with reduction in one intermidiate stage. Fault tolerance has been introduced in the form of disjoint paths formed between each source-destnation node pair. Hence reliability has been improved.Results:Terminal, Broadcast and Network Reliability has been evaluated by using Reliability Block Diagrams for each source-destination node pair. The results have been shown, which depicts the hiher reliability values for newly proposed network. The cost analysis shows that new SEGINMinus is a cheaper network than SEGIN.Conclusion:SEGIN-Minus has better reliability and Fault-tolerance than priviously proposed SEGIN.

A study of multistage interconnection networks operating with wormhole routing and equipped with multi-lane storage

Multistage interconnection networks (MINs) provide critical communication resources between network components with an attractive cost/performance relation. In this paper, a novel architecture for a MIN is proposed. In contrast to other existing networks, this new architecture operates via wormhole routing using a multi-lane equivalent-weighted fair queuing system. Associating the lane storage with each physical channel for movement of the flits allows for high levels of packet flow and makes the system more robust. The resulting flit scheduling schema has been studied thoroughly, and the results are presented in this manuscript. In addition to performance metrics, additional factors such as complexity, cost and reliability are investigated. Since a basic aim of the design of MINs is to achieve a good data flow control mechanism, this proposal is an extremely effective and robust solution. The rationale behind this innovative scheme is to introduce a more efficient network technology, thus providing a better quality of service (i.e. streaming media vs. file transfer).

Assessment of reliability and signature of Benes network using universal generating function

This paper explores the reliability and signature analysis of the multistage interconnection network, especially in a non-blocking network that can be rearranged. In general structure, blocking is a crucial problem faced by multistage interconnection networks. Hence to discuss this issue, here we have taken a most significant part of rearrangeable non-blocking networks, namely Benes network which is the utmost popular rearrangeable non-blocking multistage interconnection networks. In the current study, we propose to assess the reliability having both ‘independent and identically and non-identically distributed components’ of Benes network in the three contexts, viz. terminal, broadcast and network with the help of universal generating function. With the aid of Owen's method, an efficient algorithm was developed to enumerate the signature and mean time to failure of the Benes network having independent, identically distributed lifetime components.

A High-Performance Scalable Shared-Memory SVD Processor Architecture Based on Jacobi Algorithm and Batcher’s Sorting Network

Eigenvalue Decomposition (EVD) and Singular Value Decomposition (SVD) are two crucial transformations in many signal processing applications. The main drawback of these algorithms is their computationally intensive nature which prevents them to be efficiently exploited in high-performance, real-time and mobile applications. By extracting the inherent parallelism of the Jacobi SVD, a new parallel data distribution and access pattern for this algorithm is proposed first. Based on the proposed parallel data distribution, a novel shared-memory architecture is then proposed to support EVD/SVD computation in a high-performance and scalable manner. A new Multistage Interconnection Network based on Batcher’s odd-even merge sorting network is developed and exploited in the architecture to preserve its performance and scalability by simultaneously connecting different numbers of processing elements to the system memory hierarchy in a parallel conflict-free manner. The proposed architecture can be configured to compute EVD/SVD of matrices of arbitrary size, with different numbers of processing elements achieving a linear speed-up. The synthesis results in a 90 nm technology show that the system with one, two, and four processing elements achieves a throughput of 1.81, 3.63, and 7.26 million EVD/SVD’s per second, respectively with a frequency of 813 MHz for an $8\times 8$ matrix.

Delta Multi-Stage Interconnection Networks for Scalable Wireless On-Chip Communication

The Network-on-Chip (NoC) paradigm emerged as a viable solution to provide an efficient and scalable communication backbone for next-generation Multiprocessor Systems-on-Chip. As the number of integrated cores keeps growing, alternatives to the traditional multi-hop wired NoCs, such as wireless Networks-on-Chip (WiNoCs), have been proposed to provide long-range communications in a single hop. In this work, we propose and analyze the integration of the Delta Multistage Interconnection Network (MINs) as a backbone for wireless-enabled NoCs. After extending the well-known Noxim platform to implement a cycle-accurate model of a wireless Delta MIN, we perform a comprehensive set of SystemC simulations to analyze how wireless-augmented Delta MINs can potentially lead to an improvement in both average delay and saturation. Further, we compare the results obtained with traditional mesh-based topologies, reporting energy profiles that show an overall energy cost reduced on both wired/wireless scenarios.

Neural Network System Design for Predicting MIN Reliability

Efforts have been made to examine and study different path and multi-path Multistage Interconnection Networks (MIN) possessing regular or irregular topology. Numerous strategies for establishing fault-tolerance in MINs have also been studied. These studies have provided us help to understand the strength and weakness of the existing static and dynamic and regular and irregular MINs. Application of Neural Networks leads to the development of MINs with improved performance and study of its Reliability In this paper ANN based system has been developed which will help in the study of metrics required for enhancing and predicting the reliability of MINs. In this paper Number of iterations are conducted to improve the ANN based system to predict the reliability of MINs by changing the number of neurons and the number of layers.

A Survey of Multistage Interconnection Networks

Background: Multistage interconnection networks are being used in computer and communications. Multiprocessor architectures for parallel computing exercise these interconnection networks for connecting various processing elements and transfer data between sub-systems of a digital system. The vast diversity of the field poses an obstacle to realize different kinds of interconnection networks and their relationship. Methods: This paper consists of an extensive survey of multistage interconnection networks. Results: A broad classification of multistage interconnection networks based on network functionality, reliability and fault tolerance is presented in order to emphasize the important principles which differentiate the network architectures. For each class of network, significant results are given and the basic design principles are explained. Conclusion: The various multistage interconnection networks design provide high performance, availability, throughput, lower latency, less power consumption along with improved fault-tolerance and reliability. However, there is a rising demand for new fault-tolerant and reliable multistage interconnection networks.

Parallel SEN: a new approach to improve the reliability of shuffle-exchange network

In the past few decades, the demand for high-performance computing has been increasingly growing. These systems usually employ many processing elements working together via interconnection networks to solve complicated problems. Due to the efficiency and cost productivity, multistage interconnection networks (MINs) are recommended for use in such systems. At the same time, shuffle-exchange networks (SENs) have extensively been used as a suitable solution to multistage interconnection networks, given the size of their switching elements and simple configurations. In this paper, parallel SEN (PSEN) is proposed to enhance the reliability of these networks. Moreover, PSENs with one and two more stages (PSEN+ and PSEN+2) are utilized to optimize the reliability factor. The reliability analysis of the proposed network is performed through the reliability block diagram. According to the evaluation results, PSEN achieved higher reliability compared to SEN in different aspects of reliability, such as terminal, broadcast, and network. The proposed network also improves the cost-effectiveness in comparison with other MINs.