Abstract
The Network-on-Chip (NoC) paradigm emerged as a viable solution to provide an efficient and scalable communication backbone for next-generation Multiprocessor Systems-on-Chip. As the number of integrated cores keeps growing, alternatives to the traditional multi-hop wired NoCs, such as wireless Networks-on-Chip (WiNoCs), have been proposed to provide long-range communications in a single hop. In this work, we propose and analyze the integration of the Delta Multistage Interconnection Network (MINs) as a backbone for wireless-enabled NoCs. After extending the well-known Noxim platform to implement a cycle-accurate model of a wireless Delta MIN, we perform a comprehensive set of SystemC simulations to analyze how wireless-augmented Delta MINs can potentially lead to an improvement in both average delay and saturation. Further, we compare the results obtained with traditional mesh-based topologies, reporting energy profiles that show an overall energy cost reduced on both wired/wireless scenarios.
Highlights
Network-on-Chip (NoC) design paradigm has been one of the most promising and, over the past years, widespread solutions to implement communication interconnects able to cope with the growing requirements in terms of energy and performance of multi-/many- core architectures such as Multiprocessor Systems-on-Chip (MPSoCs) [1,2,3]
We investigate a multi-objective analysis, which takes into account delay/energy trade-off of Multistage Interconnection Networks (MINs) when compared to traditional mesh, especially when considering large NoCs augmented with alternative interconnection technologies that allow for future scalability, such as on-chip radio communications infrastructures
The analysis of the results can be conducted along with two different and orthogonal perspectives: (i ) how Delta MINs perform as compared with traditional mesh architectures, (ii ) how the wireless-augmented communication affects the average delay and saturation point for different traffic patterns and node number, regardless of the type of network
Summary
Network-on-Chip (NoC) design paradigm has been one of the most promising and, over the past years, widespread solutions to implement communication interconnects able to cope with the growing requirements in terms of energy and performance of multi-/many- core architectures such as Multiprocessor Systems-on-Chip (MPSoCs) [1,2,3]. NoC implementations can be adapted to the needs of the scenarios to be supported thanks to a whole series of features and parameters such as topology, switches architecture, buffer size, and routing strategies [4,5,6]. Multistage Interconnection Networks (MINs), traditionally proposed in high-performance parallel computing as a low-latency interconnection solution, are predicted to become more and more relevant for NoCs, mainly due to the high pin bandwidth of router chips, which motivates networks that can potentially offer a much higher node degree [11,12]. A relevant feature of MINs is that they are indirect topologies, i.e., consisting of two types of nodes: (i) terminal nodes, referred to as Processing
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