Multi-core Architectures Research Articles

Efficient Large-Scale Virtual Screening Based on Heterogeneous Many-Core Supercomputing System.

With the rapid growth of virtual drug data- bases, the need for efficient molecular docking tools for large-scale screening is also growing. We have developed Vina@QNLM 2.0, a novel molecular docking system that leverages the logical processing units and computational processing arrays of heterogeneous multicore architecture processors. Compared to Vina@QNLM, the new version optimizes the docking speed without sacrificing accuracy. This greatly improves the scoring capability for large molecules (molecular weight > 500). Simultaneously, the new system provides enhanced support for applications such as reverse target finding through an improved parallel strategy. Vina@QNLM 2.0 achieves a speedup 20 times higher than that, using logical processing units only during a single docking process. Additionally, we successfully scaled the reverse target finding a task to 122,401 kernel groups with a robust scalability of 80.01%. In practice, we completed a reverse target-seeking for nine glycan molecules with 10,094 proteins within 1 hour.

Parallel multithreaded deduplication of data sequences in nuclear structure calculations

High performance computing (HPC) applications that work with redundant sequences of data can benefit from their deduplication. We study this problem on the symmetry-adapted no-core shell model (SA-NCSM), where redundant sequences of different kinds naturally emerge in the data of the basis of the Hilbert space physically relevant to a modeled nucleus. For a fast solution of this problem on multicore architectures, we propose and present three multithreaded algorithms, which employ either concurrent hash tables or parallel sorting methods. Furthermore, we present evaluation and comparison of these algorithms based on experiments performed with real-world SA-NCSM calculations. The results indicate that the fastest option is to use a concurrent hash table, provided that it supports sequences of data as a type of table keys. If such a hash table is not available, the algorithm based on parallel sorting is a viable alternative.

Innovations in Multicore Network Processor Design for Enhanced Performance

The rapid expansion of network traffic, driven by the proliferation of internet-connected devices and the growing demand for high-speed data transmission, has intensified the need for advanced network processing capabilities. Multicore network processors have emerged as a pivotal solution to address these challenges, offering significant enhancements in performance, scalability, and efficiency. This paper explores the innovations in multicore network processor design, focusing on the architectural advancements and optimization techniques that have been instrumental in elevating their performance. One of the key innovations in multicore network processor design is the shift from traditional single-core processors to multicore architectures. This transition has allowed for parallel processing, where multiple cores can simultaneously execute different tasks, significantly increasing throughput and reducing latency. The adoption of multicore architectures has also facilitated the handling of diverse and complex workloads, which is essential in modern networking environments that demand high performance and low power consumption. A major focus of recent innovations is the optimization of core interconnects and memory hierarchies. Efficient inter-core communication is critical for maintaining high performance in multicore processors. The development of advanced interconnect technologies, such as network-on-chip (NoC) and high-bandwidth interconnects, has minimized communication bottlenecks, enabling faster data exchange between cores. Additionally, improvements in memory hierarchies, including the integration of larger caches and the use of intelligent memory management techniques, have further enhanced data access speeds and reduced memory latency, contributing to overall performance gains. Another significant area of innovation is the implementation of specialized cores within multicore processors. These specialized cores are designed to handle specific network functions, such as encryption, compression, and deep packet inspection, more efficiently than general-purpose cores. By offloading these tasks to specialized cores, the overall processing load is balanced, leading to better performance and energy efficiency. Furthermore, the integration of hardware accelerators, such as field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs), has been a critical development, providing dedicated processing power for complex tasks and further enhancing the performance of multicore network processors. Power efficiency has also been a major consideration in the design of multicore network processors. Innovations in dynamic voltage and frequency scaling (DVFS) and power gating have enabled processors to adjust their power consumption based on workload demands, reducing energy usage without compromising performance. Additionally, advances in thermal management techniques, such as improved heat dissipation methods and adaptive cooling technologies, have ensured that multicore processors can operate at peak performance levels without overheating. The integration of machine learning (ML) and artificial intelligence (AI) in multicore network processor design represents another frontier of innovation. ML algorithms can optimize resource allocation, predict traffic patterns, and dynamically adjust processing tasks to enhance performance and efficiency. AI-driven management of network processors allows for more intelligent decision-making, enabling the processors to adapt to changing network conditions in real-time, which is crucial for maintaining high performance in dynamic environments. Moreover, the increasing complexity of network security has driven innovations in multicore network processor design. Enhancements in security features, such as hardware-based encryption and real-time threat detection, have been integrated into modern processors to safeguard against evolving cyber threats. The ability to handle security tasks at the hardware level not only improves performance but also provides a robust defense mechanism against attacks, ensuring the integrity and confidentiality of data. In conclusion, the ongoing innovations in multicore network processor design are pivotal in meeting the growing demands of modern networking environments. By advancing processor architectures, optimizing interconnects and memory hierarchies, integrating specialized cores, enhancing power efficiency, and incorporating AI and security features, these processors are well-equipped to deliver superior performance and efficiency. As network demands continue to evolve, these innovations will play a crucial role in shaping the future of network processing, enabling faster, more reliable, and secure data transmission across increasingly complex networks.

In defense of extreme database-centric architecture

A famous aphorism in computer science goes: "All problems in computer science can be solved by another level of indirection", often expanded by the humorous clause "except for the problem of too many levels of indirection". After 30 years of applying the first aphorism, multi-tier architectures (i.e. architectures with many levels of indirection) have become the de facto standard for web applications, leaving little room for alternative architectures. But in the industry, there is a product to develop and run web applications that follows a different architecture, centered on the RDBMS to the extreme of not needing any other component to function. There are not many papers in academia that addresses RDBMS-centric architectures in general, and this extreme architecture in particular has not been considered. In recent works I have analyzed the case of an extreme database-centric architecture, which I have called RDBMS-only architecture. This article defends the relevance and analyzes opportunity cases of this approach.

CUDA-BASED PARALLELIZATION OF GRADIENT BOOSTING AND BAGGING ALGORITHM FOR DIAGNOSING DIABETES

Data, its volume, structure, and form of presentation are among the most significant problems in working in the medical field. The probability of error is very high without innovative high-tech data analysis tools. It is easy to miss an important factor that is critical but lost among other, less important information. This work aims to study the proposed parallel gradient boosting algorithm in combination with the Bagging algorithm in the classification of diabetes to achieve greater stability and higher accuracy, reduce computational complexity and improve performance in medicine. The methods of parallelization of the Gradient Boosting algorithm in combination with the Bagging algorithm are investigated in the paper. Performance scores were obtained: approximately 7 using ThreadPoolExecutor and an eight-core computer system and 9.5 based on CUDA technology. Performance indicators that go to the unit are calculated. This, in turn, confirms the effectiveness of the proposed parallel algorithm. Another significant result of the study is improving algorithm accuracy by increasing the number of algorithms in the composition. The problem of diagnosing a patient's diabetes based on specific measurements included in the data set is considered. Detailed analysis and pre-processing of the selected dataset were performed. The parallelization of the proposed algorithm is implemented using the multi-core architecture of modern computers and CUDA technology. The process of learning models and training samples was parallelized. The theoretical estimation of the computational complexity of the offered parallel algorithm is given. A comparison of serial and parallel algorithm execution time using ThreadPoolExecutor when varying the number of threads and algorithms in the composition is presented. And also, the comparative analysis of time expenses at consecutive and parallel execution based on CPU and GPU is carried out.

Fault-aware routing approach for mesh-based Network-on-Chip architecture

Aggressive communication among cores in multi-core architectures leads to excessive workload on the components which often degrades the normal functionality and induces faults. Network-on-Chip (NoC) also inherits the phenomenon of fault occurrence in multi-core architectures that affect the links and routers of the communication infrastructure. In this work, we emphasize on faults that occur in NoC routers and propose a fault-aware routing approach to mitigate them. The proposed routing approach selects the routing path for flits depending on the health status of the neighboring routers. Furthermore, a router cool-off mechanism is introduced so that the routers that have reached the workload threshold can be reused after some cool-off period. A router micro-architecture is also presented to support the fault-aware routing approach. While comparing with the state-of-art works, the proposed methodology achieves both zero fault occurrence and significant improvement in throughput with negligible delay overhead.

Implementation of Real-Time Space Target Detection and Tracking Algorithm for Space-Based Surveillance

Space-based target surveillance is important for aerospace safety. However, with the increasing complexity of the space environment, the stellar target and strong noise interference pose difficulties for space target detection. Simultaneously, it is hard to balance real-time processing with computational performance for the onboard processing platform owing to resource limitations. The heterogeneous multi-core architecture has corresponding processing capabilities, providing a hardware implementation platform with real-time and computational performance for space-based applications. This paper first developed a multi-stage joint detection and tracking model (MJDTM) for space targets in optical image sequences. This model combined an improved local contrast method and the Kalman filter to detect and track the potential targets and use differences in movement status to suppress the stellar targets. Then, a heterogeneous multi-core processing system based on a field-programmable gate array (FPGA) and digital signal processor (DSP) was established as the space-based image processing system. Finally, MJDTM was optimized and implemented on the above image processing system. The experiments conducted with simulated and actual image sequences examine the accuracy and efficiency of the MJDTM, which has a 95% detection probability while the false alarm rate is 10−4. According to the experimental results, the algorithm hardware implementation can detect targets in an image with 1024 × 1024 pixels in just 22.064 ms, which satisfies the real-time requirements of space-based surveillance.

Parallelism in a Region Inference Context

Region inference is a type-based program analysis that takes a non-annotated program as input and constructs a program that explicitly manages memory allocation and deallocation by dividing the heap into a stack of regions, each of which can grow and shrink independently from other regions, using constant-time operations. Whereas region-based memory management has shown useful in the contexts of explicit region-based memory management, and in particular, in combination with parallel execution of code, combining region inference with techniques for higher-order parallel programming has not been investigated. In this paper, we present an implementation of a fork-join parallel construct suitable for a compiler based on region inference. We present a minimal higher-order language incorporating the parallel construct, including typing rules and a dynamic semantics for the language, and demonstrate type soundness. We present a novel effect-based region-protection inference algorithm and discuss benefits and shortcomings of the approach. We also describe an efficient implementation embedded in the MLKit Standard ML compiler. Finally, we evaluate the approach and the implementation based on a number of parallel benchmarks, and thereby demonstrate that the technique effectively utilises multi-core architectures in a higher-order functional setting.

Implementation of Fully-Pipelined CNN Inference Accelerator on FPGA and HBM2 Platform

Many deep convolutional neural network (CNN) inference accelerators on the field-programmable gate array (FPGA) platform have been widely adopted due to their low power consumption and high performance. In this paper, we develop the following to improve performance and power efficiency. First, we use a high bandwidth memory (HBM) to expand the bandwidth of data transmission between the off-chip memory and the accelerator. Second, a fully-pipelined manner, which consists of pipelined inter-layer computation and a pipelined computation engine, is implemented to decrease idle time among layers. Third, a multi-core architecture with shared-dual buffers is designed to reduce off-chip memory access and maximize the throughput. We designed the proposed accelerator on the Xilinx Alveo U280 platform with in-depth Verilog HDL instead of high-level synthesis as the previous works and explored the VGG-16 model to verify the system during our experiment. With a similar accelerator architecture, the experimental results demonstrate that the memory bandwidth of HBM is 13.2× better than DDR4. Compared with other accelerators in terms of throughput, our accelerator is 1.9×/1.65×/11.9× better than FPGA+HBM2 based/low batch size (4) GPGPU/low batch size (4) CPU. Compared with the previous DDR+FPGA/DDR+GPGPU/DDR+CPU based accelerators in terms of power efficiency, our proposed system provides 1.4-1.7×/1.7-12.6×/6.6-37.1× improvement with the large-scale CNN model.

Mdapy: A flexible and efficient analysis software for molecular dynamics simulations

The mdapy is a library for pre- and postprocessing molecular dynamics simulation data. Benefitting from the just-in-time compile technology of TaiChi mdapy can be written in pure Python while possessing similar speed to those written in C++. mdapy is designed with highly paralleled and makes full advantages of modern computer resources on both multicore CPU and GPU architecture. The package implements a fast module to find the neighbors of particles in both free and periodic boundaries, based on which it offers a wide variety of methods to analyze atomic environments, such as standard centrosymmetry parameters, radial distribution function and newer methods, such as atomic entropy fingerprint. In addition, mdapy can be used to create the geometric structure of polycrystals with metallic or graphene grain boundaries by Voronoi diagram. mdapy can directly read the DUMP and DATA format defined in LAMMPS code, and, in practice, it accepts any other format by converting it into NumPy ndarray format. This design philosophy enables seamless integration with abundant scientific ecosystems in the Python community and easy cooperation with other analysis codes like OVITO or freud. Program summaryProgram Title: mdapyCPC Library link to program files:https://doi.org/10.17632/dtdkxvcsc9.1Developer's repository link:https://github.com/mushroomfire/mdapyCode Ocean capsule:https://codeocean.com/capsule/5271472Licensing provisions: BSD 3-clauseProgramming language: Python, C++Nature of problem: Atomic environment analysis and generation of the initial structure are important in molecular dynamics simulations. Many analysis methods relying on particle neighbors, such as radial distribution functions and atomic entropy, are computationally intensive and need to be carefully implemented to scale to large systems. Traditional code is often written in C++ or Fortran to guarantee performance while causing difficulty in installation and secondary development due to the complexity of the programming language.Solution method: mdapy is written in parallel to quickly perform neighbor finding, provides a set of analysis methods and creates an atomic geometry structure on multicore CPU and GPU. Over 95 percent of mdapy is written in Python with a uniform API to call. All data are stored in NumPy ndarray, making users easy to install, use and secondary develop.Additional comments including restrictions and unusual features:1. mdapy provides fast parallel implementations of neighbor finding in periodic and free boundary system.2. mdapy can generate a polycrystalline model with graphene grain boundaries.3. mdapy is helpful for analyzing the melting process by the mean squared displacement and Lindemann index at the atomic level.4. mdapy is very easy to install via pip install mdapy without any compile steps and can be run on Windows, Linux and Mac OS with Python 3.7-3.10.5. mdapy has detailed documentation to make it easier to use.

Development an efficient AXI-interconnect unit between set of customized peripheral devices and an implemented dual-core RISC-V processor

RISC-V set architecture is playing an increasingly important role in processor technology due to its open instructions which allow researchers to build and improve computing systems. However, many RISC-V architectures exist in multi-core architecture with complex designs, large area, and high-power consumption. This paper studies an open-source multi-core RISC-V processor in a simple design with less power consumption. The processor depends on an open-source single RISC-V core processor, Taiga. Two cores of Taiga are integrated on a single chip while addressing issues related to cache coherence, interconnect, and memory design. A solution has been developed to achieve data coherence between implemented caches and the main memory; its architecture depends on the snoopy protocol. A hardware-customized peripheral unit has been implemented to achieve the management process among operated cores’ tasks. For more consistent and highly controlled memory storage, the main memory unit has been designed in dual-port based on a specific protocol in the interface, and 8192 lines and word addressable unit. As the UART is common in several devices and processors for communication, the UART as a peripheral customized device has been appended for communication with other devices. The processor has been implemented in System Verilog HDL and extensively tested on various testbenches to ensure correct functionality. Hence, the system performance has been evaluated using the CoreMark benchmark, and achieved 4.605 CoreMark/MHz on Zedboard (FPGA Xilinx family) with a maximum operating frequency 98 MHz. The results indicate that the processor performs comparably to state-of-the-art multi-core processors, while offering a simpler and more power-efficient design. Overall, the research demonstrates the potentialof RISC-V architecture in creating a simple and power-efficient multi-core RISC-V processor.

Performance aware shared memory hierarchy model for multicore processors

Despite the fact that multicore processors have a better instruction execution speed and lower power consumption, they also encounter a set of design challenges. The appearance of multicore and many core architectures has raised the problem of managing shared hierarchical memory systems. The main focus of this paper is to evaluate the behavior of shared hierarchical memory systems by modeling their response time analytically. Since the gap between the memory and processor speed increases rapidly, it gets more crucial to find an analytical model that includes the significant factors that affect the performance of hierarchical memory systems. The proposed model considers the interdependence between different memory layers and differentiates between the memory response time and memory system time. Moreover, the model evaluates the effect of memory hierarchy on the variance of the memory access time. The existence of a large variance can lead to extremely long wait queues which can dramatically affect the performance of multicore processors

Precise Event Sampling on AMD Versus Intel: Quantitative and Qualitative Comparison

Precise event sampling is a profiling feature in commodity processors that can sample hardware events and accurately locate the instructions that trigger the events. This feature has been used in a large number of tools to detect application performance issues. Although precise event sampling is readily supported in modern multicore architectures, vendor supports exhibit great differences that affect their accuracy, stability, overhead, and functionality. This work presents the most comprehensive study to date on benchmarking the event sampling features of Intel PEBS and AMD IBS and performs in-depth analysis on key differences through series of microbenchmarks. Our qualitative and quantitative analysis shows that PEBS allows finer-grained and more accurate sampling of hardware events, while IBS offers richer set of information at each sample though it suffers from lower accuracy and stability. Moreover, OS signal delivery, which is a common method used by the profiling software, introduces significant time overhead to the original overhead incurred by the hardware mechanisms in both PEBS and IBS. We also found that both PEBS and IBS have bias in sampling events across multiple different locations in a code. Lastly, we demonstrate how our findings on microbenchmarks under different thread counts hold for a full-fledged profiling tool that runs on the state-of-the-art Intel and AMD machines. Overall our detailed comparisons serve as a great reference and provide invaluable information for hardware designers and profiling tool developers.

History and Future Trends of Multicore Computer Architecture

The multicore technology concept is centered on the parallel computing possibility that can boost computer efficiency and speed by integrating two or more CPUs (Central Processing Units) in a single chip. A multicore architecture places multiple processor cores and groups them as one physical processor. The primary goal is to develop a system that can handle and complete more than one task at the same time, thereby getting a better system performance in general. This paper will describe the history and future trends of multicore computer architecture.

Digital health in smart cities: Rethinking the remote health monitoring architecture on combining edge, fog, and cloud.

Smart cities that support the execution of health services are more and more in evidence today. Here, it is mainstream to use IoT-based vital sign data to serve a multi-tier architecture. The state-of-the-art proposes the combination of edge, fog, and cloud computing to support critical health applications efficiently. However, to the best of our knowledge, initiatives typically present the architectures, not bringing adaptation and execution optimizations to address health demands fully. This article introduces the VitalSense model, which provides a hierarchical multi-tier remote health monitoring architecture in smart cities by combining edge, fog, and cloud computing. Although using a traditional composition, our contributions appear in handling each infrastructure level. We explore adaptive data compression and homomorphic encryption at the edge, a multi-tier notification mechanism, low latency health traceability with data sharding, a Serverless execution engine to support multiple fog layers, and an offloading mechanism based on service and person computing priorities. This article details the rationale behind these topics, describing VitalSense use cases for disruptive healthcare services and preliminary insights regarding prototype evaluation.

A shared libraries aware and bank partitioning-based mechanism for multicore architecture

A shared libraries aware and bank partitioning-based mechanism for multicore architecture

Load balanced locality-aware parallel SGD on multicore architectures for latent factor based collaborative filtering

We investigate the parallelization of Stochastic Gradient Descent (SGD) for matrix completion on multicore architectures. We provide an experimental analysis of current SGD algorithms to find out their bottlenecks and limitations. Grid-based methods suffer from load imbalance among 2D blocks of the rating matrix, especially when datasets are skewed and sparse. Asynchronous methods, on the other hand, can face cache issues due to their memory access pattern. We propose bin-packing-based block balancing methods that are alternative to the recently proposed BaPa method. We then introduce Locality Aware SGD (LASGD), a grid-based asynchronous parallel SGD algorithm that efficiently utilizes cache by changing nonzero update sequence without affecting factor update order and carefully arranging latent factor matrices in the memory. Combined with our proposed load balancing methods, our experiments show that LASGD performs significantly better than alternative approaches in parallel shared-memory systems.

Precise event sampling‐based data locality tools for AMD multicore architectures

SummaryWe propose ComDetective, an inter‐thread communication analyzer, and ReuseTracker, a reuse distance analyzer, that leverage the hardware features in AMD processors to support low‐overhead profiling. Both tools employ the instruction‐based sampling (IBS) facility and debug registers in AMD processors to detect inter‐thread communication and data reuse. Different from prior arts, ComDetective differentiates the communication into true and false sharing, and ReuseTracker measures reuse distance in private and shared caches by also considering cache line invalidation with low overhead. Both tools can attribute the communications and reuses to source code lines. To our knowledge these tools are two of the few profiling tools designed specifically for AMD x86 architectures using IBS. Our tools are timely and relevant considering the rise in numbers of AMD processor based data centers and HPC systems. We perform experiments to evaluate the accuracy and overheads of the proposed tools on an AMD machine with two‐socket EPYC 7352 processors. ComDetective exhibits high accuracy while introducing 5.14 runtime and 1.4 memory overheads. ReuseTracker also displays high accuracy, which is 95%, with 11.76 runtime and 1.46 memory overheads. These overheads are much lower than the overheads of existing simulators and code instrumentation‐based tools. Lastly, we demonstrate the usage of the tools by having ComDetective and ReuseTracker facilitate the code refactoring of two data mining benchmarks to improve their performance by up to 29%.

Digital Transformation of Resource Management of Territorial Communities Based on the Cloud ERP System in the Concept of Industry 4.0

The aim of this study is to explore the potential for creating a unified digital information space using a modern ERP system to manage all processes and resources of territorial communities, which are categorized as non-industrial enterprises. This research is conducted in the context of building a modern landscape of Industry 4.0 technologies, which are considered to be the future of industrialization. The practical case of Ukraine is used to illustrate the typical problems associated with the uncoordinated use of different types of software in the management of enterprises and organizations operating in territorial communities. Furthermore, the advantages of switching to a new ERP platform are discussed. The benefits of deploying the system's multi-tier architecture in the cloud and implementing a corporate model for parallel management of individual divisions and organizations are also highlighted.

Communication Latency and Power Consumption Consequence in Multi-Core Architectures and Improvement Methods

The present electronics world has a lot of dependency on processing devices in the current and future developments. Even non-electronic industries have much data to process and are indirectly dependent on processors. The larger the number of processors incorporated into the architecture, will lower the data handling and processing time; thus, efficiency improves. Hence multi-core processors have become a regular part of the design of processing elements in the electronic industry. The large number of processors incorporated into the system architecture results in difficulty in communicating among them without a deadlock or live lock. NoC is a promising solution for communicating among the on-chip processors, provided it is fast enough and consumes less energy. Further, the latency among the multi-core processors should be optimal to stand with the increasing data acquisition and processing in the new/developing operating systems and software. This paper addresses energy efficiency and latency reduction methods/techniques for Multi-core architectures.