Multiprocessor System-on-chip Research Articles

An Optimized Weighted Average Makespan in Fault-Tolerant Heterogeneous MPSoCs

The multiprocessor system on chips (MPSoCs) are considered today the core of most modern systems. Most of the applications of these heterogeneous MPSoCs include critical systems and hence terms of fault tolerance and reliability have become essential. Task replication is a technique to carry out fault tolerance and can help for reducing the schedule length by increasing locality. It introduces an upper and lower bound for the makespan of each schedule while each task is replicated more than once. If a fault occurs during execution, the expected makespan will be some value between the upper bound and the lower bound based on when and where the fault has occurred. In this research a new performance parameter namely the weighted average makespan is introduced. It is calculated as the average of the lower and upper bounds of makespan using the probability of occurrence of each. Two scheduling algorithms are presented for fault tolerant scheduling based on directed acyclic graphs. These algorithms are the list scheduling algorithm and the optimizing of the weighted average makespan based on simulated annealing method. The simulation results show that the techniques can improve the schedule length and increase the system reliability without compromising the performance.

Exploring the security landscape: NoC-based MPSoC to Cloud-of-Chips

In this paper, we present a detailed and systematic overview of communication security aspects of Multi-Processor Systems-on-Chip (MPSoC) and the emerging potential threats on the novel Cloud-of-Chips (CoC) paradigm. The CoC concept refers to highly scalable and composable systems, assembled not only at system design-time using RTL, like traditional SoC, but also at integrated circuit (IC) packaging time thanks to 3D-IC integration technology. Practical implementation of CoC systems needs to solve the problem of scalable, configurable and secure communication not only between different functional blocks in a single ICs, but also between different ICs in a single package, and between different packages on the same or different PCBs and even between different systems. To boost such extremely flexible communication infrastructure CoC system relies on Software-Defined Network-on-Chip (SDNoC) paradigm that combines design-time configurability of on-chip systems (NoC) and highly configurable communication of macroscopic systems (SDN). This study first explores security threats and existing solutions for traditional MPSoC platforms. Afterwards, we propose SDNoC as an alternative to MPSoC communication security, and we further extend our discussion to CoC systems to identify additional security concerns. Moreover, we present a comparison of SDNoC based approach over existing approaches and discuss its potential advantages.

A metadata-driven approach to efficiently detect code-reuse attacks on ARM multiprocessors

In recent years, there is a growing need to protect security and privacy of the data against various attacks on software running on smart mobile devices. As of today, the code-reuse attack (CRA) is known as one of the most sophisticated techniques. We in this paper propose a hardware-assisted solution that can be practically deployed into the existing ARM-based mobile devices. We exploit CoreSight debug interface to obtain the core internal information. As the information fed from the debug interface is insufficient for our purpose to detect CRAs, our solution uses the metadata to supplement the lacking information. However, most metadata-driven approaches suffer from the significant storage overhead to store every basic information describing the original data that is vital to their analysis or techniques. As this large space overhead can be a major obstacle to the general acceptance of our solution in ARM-based devices with strict performance constraints, we have endeavored to develop a technique minimizing the memory overhead. Also, we have extended our solution to apply to multiprocessor SoCs as the growing number of computing systems including mobile devices use multiprocessor architectures. Experimental results show that our solution detects CRAs with 1.74% performance overhead in dual-CPU system and requires only 5.66% more memories for storing metadata.

Congestion‐Aware Routing Algorithm for NoC Using Data Packets

Network on Chip (NoC) is a communication framework for the Multiprocessor System on Chip (MPSoC). It is a router‐based communication system. In NoC architecture, nodes of MPSoC are communicating through the network. Different routing algorithms have been developed by researchers, e.g., XY, intermittent XY, DyAD, and DyXY. The main problems in these algorithms are congestion and faults. Congestion and faults cause delay, which degrades the performance of NoC. A congestion‐aware algorithm is used for the distribution of traffic over NoC and for the avoidance of congestion. In this paper, a congestion‐aware routing algorithm is proposed. The algorithm works by sending congestion information in the data packet. The algorithm is implemented on a 4 × 4 mesh NoC using FPGA. The proposed algorithm decreases latency, increases throughput, and uses less bandwidth in sharing congestion information between routers in comparison to the existing congestion‐aware routing algorithms.

A Survey on the Security of Wired, Wireless, and 3D Network-on-Chips

Network-on-Chips (NoCs) have been widely used as a scalable communication solution in the design of multiprocessor system-on-chips (MPSoCs). NoCs enable communications between on-chip Intellectual Property (IP) cores and allow processing cores to achieve higher performance by outsourcing their communication tasks. NoC paradigm is based on the idea of resource sharing in which hardware resources, including buffers, communication links, routers, etc., are shared between all IPs of the MPSoC. In fact, the data being routed by each NoC router might not be related to the router's local core. Such a utilization-centric design approach can raise security issues in NoC-based designs, e.g., integrity and confidentiality of the data being routed in an NoC might be compromised by unauthorized accesses/modifications of intermediate routers. Many papers in the literature have discovered and addressed security holes of NoCs, aiming at improving the security of the NoC paradigm. However, to the best of our knowledge, there is no solid survey study on the security vulnerabilities and countermeasures for NoCs. This paper will review security threats and countermeasures proposed so far for wired NoCs, wireless NoCs, and 3D NoCs. The paper aims at giving the readers an insight into the attacks and weaknesses/strengths of countermeasures.

An Approach for Power Estimation at Electronic System Level using Distributed Simulation

The present research aims to develop an approach using HLA (High Level Architecture), enabling the cre-ation of a distributed and heterogeneous environment, composed by different tools and models to obtain a better trade-off between accuracy and run time in power estimation. These models can be described in different languages and/or abstraction levels, as well as use different power estimation approaches. The use of HLA enables the synchronized and distributed simulation of the elements that compose the simulation environment. The approach must allow the collecting and grouping of power estimation data in a centralized manner. As a case study, an MPSoC (MultiProcessor System-on-Chip) ESL/TLM model, described in C++/SystemC, and an ESL model, created on Ptolemy framework, have been used. The experimental results show the flexibility of the approach, which promotes an integrated view of power estimation data.

Review of Network on Chip Routing Algorithms

System on chip (SoC) is an integrated circuit in which components are communicating through the bus interconnection system. Network on chip (NoC) is a communication network for a multiprocessor system on chip (MPSoC). In NoC architecture node/ component of MPSOC are co

Energy and Performance Trade-Off Optimization in Heterogeneous Computing via Reinforcement Learning

This paper suggests an optimisation approach in heterogeneous computing systems to balance energy power consumption and efficiency. The work proposes a power measurement utility for a reinforcement learning (PMU-RL) algorithm to dynamically adjust the resource utilisation of heterogeneous platforms in order to minimise power consumption. A reinforcement learning (RL) technique is applied to analyse and optimise the resource utilisation of field programmable gate array (FPGA) control state capabilities, which is built for a simulation environment with a Xilinx ZYNQ multi-processor systems-on-chip (MPSoC) board. In this study, the balance operation mode for improving power consumption and performance is established to dynamically change the programmable logic (PL) end work state. It is based on an RL algorithm that can quickly discover the optimization effect of PL on different workloads to improve energy efficiency. The results demonstrate a substantial reduction of 18% in energy consumption without affecting the application’s performance. Thus, the proposed PMU-RL technique has the potential to be considered for other heterogeneous computing platforms.

An MPI-based MPSoC Platform in FPGA

The increase in the level of integration of components on silicon became possible to build systems with multiple processors on a single chip. These systems are named MPSoCs (Multi-Processor Systems-on-Chip), and some of them use Networks-on-Chip (NoC) as the communication infrastructure to interconnect their components. This work presents an MPSoC platform designed for performance evaluation of an NoC in FPGA. The platform relies on the use of 32-bit programmable processors and an MPI (Message Passing Interface) communication library, providing a flexible infrastructure for traffic generation and analysis, and enabling the development of parallel applications. For evaluation, we implemented a proof-of-concept instance of the proposed platform in FPGA, and the experimental results show that the software layer of the communication infrastructure dominates communication latency.

MeXT-SE: A Design Tool to Transparently Generate Secure MPSoC

Hardware accelerators are increasingly employed in conjunction with general-purpose processors to meet stringent performance constraints. In these heterogeneous systems, security has become a prime concern. In this article, we present a design approach to generate platform-independent secure multiprocessor systems-on-chip (MPSoC) from a high-level abstraction. The aim of this article is to simplify the implementation of MPSoC, while ensuring security. The proposed design flow starts with a set of abstract and concrete specifications of a system, provided by the user, and ends up generating a generic description of the appropriate hardware design by setting up the communication structure of different components. The resulting abstract architecture is further processed using the vendor tool-chain to generate the target platform’s configuration. To enforce security, we proposed a distributed isolation framework for multilevel security, resource assess control including access to and from hardware accelerators. From a user specification, the security layer is transparently generated and security rules and requirements transparently enforced at run-time. Experimentation results show that our proposed tool can generate MPSoC designs capable of providing secure hardware execution with negligible execution overhead.

Network-on-Chip Intellectual Property Protection Using Circular Path--based Fingerprinting

Intellectual property (IP) reuse is a well-known technique in chip design industry. But this technique also exposes a security vulnerability called IP stealing attack. Network-on-Chip (NoC) is an on-chip scalable communication medium and is used as an IP and sold by various vendors to be integrated in a Multiprocessor System-on-Chip (MPSoC). An attacker can launch IP stealing attack against NoC IP. In this article, we propose a NoC IP protection technique called circular path--based fingerprinting (CPF) using fingerprint embedding. We also provide a theoretical model using polyomino theory to get the number of distinct fingerprints in a NoC. We show that our proposed technique requires much less hardware overhead compared to an existing NoC IP security solution and also provides better security against removal and masking attacks. In particular, our proposed CPF technique requires 27.41% less router area compared to the existing solution. We also show that our CPF solution does not affect the normal packet latency and hence does not degrade the NoC performance.

Unified System Network Architecture: Flexible and Area-Efficient NoC Architecture with Multiple Ports and Cores

In recent years, as semiconductor manufacturing processes have been steadily scaled down, the transistor count fabricated on a single silicon die can reach up to a billion units. Therefore, current multiprocessor system-on-chips (MPSoCs) can include up to hundreds or even thousands of cores and additional accelerators for high-performance systems. Network-on-chips (NoCs) have become an attractive solution for interconnects, which are critical components of MPSoCs in terms of system performance. In this study, a highly flexible and area-efficient NoC architecture, namely the unified system network architecture (USNA), which can be tailored for various topologies, is proposed. The USNA provides high flexibility in port placements with varying numbers of local cores and router linkers. It also supports quality of service operations for both the router and linker. The network performance (e.g., average latency and saturated throughput) and implementation cost of the USNA, using various network configurations for the same number of local cores under uniform random traffic conditions, were investigated in this study. According to the simulation results, the performance of the USNA is better or similar to other NoCs, with a significantly smaller area and lower power consumption.

HRM: Merging Hardware Event Monitors for Improved Timing Analysis of Complex MPSoCs

The performance monitoring unit (PMU) in multiprocessor system-on-chips (MPSoCs) is at the heart of the latest measurement-based timing analysis techniques in critical embedded systems. In particular, hardware event monitors (HEMs) in the PMU are used as building blocks in the process of budgeting and verifying software timing by tracking and controlling access counts to shared resources. While the number of HEMs in current MPSoCs reaches hundreds, they are read via performance monitoring counters whose number is usually limited to 4-8, thus requiring multiple runs of each experiment in order to collect all desired HEMs. Despite the effort of engineers in controlling the execution conditions of each experiment, the complexity of current MPSoCs makes it arguably impossible to completely remove the noise affecting each run. As a result, HEMs read in different runs are subject to different variability, and hence, those HEMs captured in different runs cannot be “blindly” merged. In this work, we focus on the NXP T2080 platform where we observed up to 59% variability across different runs of the same experiment for some relevant HEMs (e.g., processor cycles). We develop a HEM reading and merging (HRM) approach to join reliably HEMs across different runs as a fundamental element of any measurement-based timing budgeting and verification technique. Our method builds on order statistics and the selection of an anchor HEM read in all runs to derive the most plausible combination of HEM readings that keep the distribution of each HEM and their relationship with the anchor HEM intact.

Security-Critical Energy-Aware Task Scheduling for Heterogeneous Real-Time MPSoCs in IoT

Internet of Things (IoT) devices, such as intelligent road side units and video-based detectors, are being deployed in emerging applications like sustainable and intelligent transportation systems. The primary obstacles against the development of these IoT devices are various security threats and huge energy consumption. In this article, we study the problem of scheduling tasks onto a heterogeneous multiprocessor system on a chip (MPSoC) deployed in IoT for optimizing quality of security under energy, real-time, and task precedence constraints. We first provide a mixed-integer linear programming (MILP) formulation for allocating and scheduling dependent tasks with energy and real-time constraints on a heterogeneous MPSoC system to maximize system quality of security. In order to efficiently solve the formulated MILP, we then propose an analysis-based two-stage scheme that determines the allocation, operating frequency, and security service of tasks to maximize system quality of security while satisfying the design constraints. We finally carry out extensive simulation experiments to validate our proposed two-stage scheme and MILP approach. Simulation results demonstrate that the proposed two-stage scheme outperforms a number of representative existing approaches in saving energy and improving system quality of security. The results also show that the proposed MILP approach can achieve the best performance and the proposed two-stage scheme has a close performance to the MILP approach.

Automatic Generation of Heterogeneous SoC Architectures With Secure Communications

Heterogeneous multiprocessor system-on-chip (MPSoC) architectures allow designers to achieve energy efficiency and high performance, especially when tailored for the target applications. This specialization requires to select the MPSoC components and define their interconnections (on the architecture side), and also to determine the mapping and scheduling of tasks and communications (on the application side). This problem is exacerbated by the growing privacy and security concerns when these architectures elaborate sensitive data. We propose a co-design solution based on ant colony optimization that also protects the exchange of private data among components. Our solution generates architectures with secure communications with systematically better performance than architectures with predefined security solutions.

P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA

The network-on-chip (NoC) has emerged as an efficient and scalable communication fabric for chip multiprocessors (CMPs) and multiprocessor system on chips (MPSoCs). The NoC architecture, the routers micro-architecture and links influence the overall performance of CMPs and MPSoCs significantly. We propose P-NoC: an FPGA-based parameterized framework for analyzing the performance of NoC architectures based on various design decision parameters in this paper. The mesh and a multi-local port mesh (ML-mesh) topologies have been considered for the study. By fine-tuning various NoC parameters and synthesizing on the FPGA, identify that the performance of NoC architectures are influenced by the configuration of router parameters and the interconnect. Experiments show that the flit width, buffer depth, virtual channels parameters have a significant impact on the FPGA resources. We analyze the performance of the NoCs on six traffic patterns viz., uniform, bit shuffle, random permutation, transpose, bit complement and nearest neighbor. Configuring the router and the interconnect parameters, the ML-mesh topology yields 75% lesser utilization of FPGA resources compared to the mesh. The ML-mesh topology shows an improvement of 33.2% in network latency under localized traffic pattern. The mesh and ML-mesh topologies have 0.53 $$\times$$ and 0.1 $$\times$$ higher saturation throughput under nearest neighbor traffic compared to uniform random traffic.

Task mapping and flow priority assignment of real-time industrial applications for network-on-chip based design

Network-on-chip (NoC) is a paradigm shift for communication between cores in multi-processor systems. It has emerged as a solution for addressing the limitations of bus-based communication in multi-processor system design. The use of MPSoC (Multi-Processor System on Chip) based design of real-time safety-critical embedded systems (such as, Avionics, Automotive etc.) is really a challenge because of the requirement of time predictability and reliability of highest degree. Task mapping and flow priority assignment are two crucial steps for real-time NoC design. Most of the earlier work on priority assignment for on-chip communications are either based on exhaustive search or are heuristic in nature.In this paper, a search based explorative solution to the priority assignment problem has been proposed with a Genetic Algorithm (GA) based formulation that uses experimentally determined heuristics to converge faster with a better solution. Unlike other works in the area, proposed work considers the task execution time while assigning flow priorities. The paper proposes a combined priority assignment and task mapping solution. The approach has been validated with two real-time industrial applications - one from automotive domain, while the other one is from avionics.

Exploring and evaluating reliable communication in optical networks-on-chip using group counting method

The optical networks-on-chip (ONoCs) are gradually becoming the most promising candidate in multiprocessor systems-on-chip (MPSoCs). To further improve the reliability of information transmission by realizing error detection in the optical communication systems on-chip, the optical channel coding technology can be exploited into the ONoCs. In this paper, a novel silicon micro-ring resonators (MRs)-based optical group counting check technology is presented. Based on the proposed optical group counting check generator and calibration circuit, an on-chip optical information transmission mechanism with error detection retransmission is proposed and analyzed. In addition, the availability of the proposed method is verified during a case study in torus-based ONoCs with wavelength division multiplexing (WDM) using Crux optical router. The simulation results show that the proposed method can effectively improve the communication reliability of the ONoCs, significantly reduce the bit error rate (BER), and increase the Q factor. For example, when the network size of the WDM-based torus ONoCs is 6 × 5, the BER and Q factor of this network using group counting method with retransmission mechanism are 4.33×10−10 and 6.10, which are respectively 3.916×10−7 lower and 1.22 higher than the traditional WDM-based torus ONoCs communication. It follows that this work can greatly improve the reliability of optical information transmission, and then achieve the scale expansion of WDM-based ONoCs.

Evaluating the computational performance of the Xilinx Ultrascale+ EG Heterogeneous MPSoC

The emergent technology of Multi-Processor System-on-Chip (MPSoC), which combines heterogeneous computing with the high performance of Field Programmable Gate Arrays (FPGAs) is a very interesting platform for a huge number of applications ranging from medical imaging and augmented reality to high-performance computing in space. In this paper, we focus on the Xilinx Zynq UltraScale+ EG Heterogeneous MPSoC, which is composed of four different processing elements (PE): a dual-core Cortex-R5, a quad-core ARM Cortex-A53, a graphics processing unit (GPU) and a high end FPGA. Proper use of the heterogeneity and the different levels of parallelism of this platform becomes a challenging task. This paper evaluates this platform and each of its PEs to carry out fundamental operations in terms of computational performance. To this end, we evaluate image-based applications and a matrix multiplication kernel. On former, the image-based applications leverage the heterogeneity of the MPSoc and strategically distributes its tasks among both kinds of CPU cores and the FPGA. On the latter, we analyze separately each PE using different matrix multiplication benchmarks in order to assess and compare their performance in terms of MFlops. This kind of operations are being carried out for example in a large number of space-related applications where the MPSoCs are currently gaining momentum. Results stand out the fact that different PEs can collaborate efficiently with the aim of accelerating the computational-demanding tasks of an application. Another important aspect to highlight is that leveraging the parallel OpenBLAS library we achieve up to 12 GFlops with the four Cortex-A53 cores of the platform, which is a considerable performance for this kind of devices.

Using Smart Routing for Secure and Dependable NoC-Based MPSoCs

The Internet-of-Things (IoT) boosted the building of computational systems that share computation, communication and storage resources for uncountable types of applications. MultiProcessor System-on-Chip (MPSoC) is a fundamental component of such systems offering large parallelism degree in an ocean of processors and memories connected through one or more Network-on-Chips (NoCs). Therefore, a massive quantity of sensitive information of several applications can share computation and communication resources of the MPSoCs demanding security mechanisms and policies. Besides, the advances of CMOS technologies increases the quantity of static and dynamic faults, requiring a dependable and resilient target architecture, which can be partially fulfilled by an effective and efficient NoC design. This work addresses fault tolerance and security at NoC level with SDR, a routing algorithm that includes the concept of security zones in the MPSoC while providing support for dependable routing avoiding faulty links. The proposed routing algorithm prioritizes communication paths deemed secure in 2D mesh NoCs with deadlock freedom. Experimental results employing realistic workload scenarios based on the NASA Numeric Aerodynamic Simulation (NAS) Parallel Benchmark (NPB) and a fault model for 65nm and 22nm CMOS fabrication technologies demonstrates the scalability, security, and dependability of SDR.