Energy and Performance Trade-Off Optimization in Heterogeneous Computing via Reinforcement Learning

Zheqi Yu,Amir M. Abdulghani,Qammer H. Abbasi,Adnan Zahid,Pedro Machado,Muhammad A. Imran,Hadi Heidari,Kia Dashtipour

doi:10.3390/electronics9111812

Zheqi Yu, Amir M. Abdulghani + Show 6 more

Open Access

https://doi.org/10.3390/electronics9111812

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Abstract

This paper suggests an optimisation approach in heterogeneous computing systems to balance energy power consumption and efficiency. The work proposes a power measurement utility for a reinforcement learning (PMU-RL) algorithm to dynamically adjust the resource utilisation of heterogeneous platforms in order to minimise power consumption. A reinforcement learning (RL) technique is applied to analyse and optimise the resource utilisation of field programmable gate array (FPGA) control state capabilities, which is built for a simulation environment with a Xilinx ZYNQ multi-processor systems-on-chip (MPSoC) board. In this study, the balance operation mode for improving power consumption and performance is established to dynamically change the programmable logic (PL) end work state. It is based on an RL algorithm that can quickly discover the optimization effect of PL on different workloads to improve energy efficiency. The results demonstrate a substantial reduction of 18% in energy consumption without affecting the application’s performance. Thus, the proposed PMU-RL technique has the potential to be considered for other heterogeneous computing platforms.

Highlights

In an embedded system, conventional strategies of low power consumption techniques slow down the processor’s running speed to reduce power consumption
The traditional dynamic voltage frequency scaling (DVFS) [2] and adaptive voltage scaling (AVS) [3] techniques are focused on the collaborative architecture of an ARM processing system (PS) [4]
We aimed to provide a framework for hardware simulation to validate and evaluate the performance and power consumption balance of the Xilinx ZYNQ multi-processor systems-on-chip (MPSoC) platform

Summary

Introduction

Conventional strategies of low power consumption techniques slow down the processor’s running speed to reduce power consumption. Power-efficient computing platforms require higher energy efficiency rather than power saving. On a downside, reducing power consumption usually affects the performance efficiency and completion of tasks takes more time due to this performance degradation [1]. At present, embedded systems have been employed to perform multiple computer intensive operations, which demand higher performance and power efficiency. Controlling energy consumption is essential for the effective performance of embedded systems. The traditional dynamic voltage frequency scaling (DVFS) [2] and adaptive voltage scaling (AVS) [3] techniques are focused on the collaborative architecture of an ARM processing system (PS) [4]

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