Multiprocessor Systems Research Articles

Development and Validation of Analytical HPLC Method for Identification and Assay of Enoxaparin Sodium in Injectable Preparations

Introduction. Enoxaparin sodium-containing drugs are included in relevant protocols for COVID-19 therapy. An increase in the production volume of such drugs leads to a demand for available and precise methods of identification and quantitative measurement of the active ingredient in the preparations. Considering the fact that pharmacopoeial methods require significant amount of expensive standards and reagents that are unavailable for numerous laboratories, it is relevant to develop a more available method that will accelerate and make cheaper the process of quality control for enoxaparin sodium-containing preparations.Aim. To develop and validate a simple, economic, and precise method of gel-permeation HPLC with the application of a refractive index detector for the evaluation of enoxaparin sodium in preparations for injection.Materials and methods. Samples of enoxaparin sodium-containing substances and commercial preparations were studied. The identification and quantitative content of the active ingredient were performed by the method of gel-permeation HPLC using a 1260 Infinity (Agilent Technologies, USA) chromatograph equipped with a refractive index detector.Results and discussion. The authors analyzed standard validation characteristics: specificity, linearity, precision, and accuracy of the method. The analysis revealed high specificity and suitability of the proposed method to chromatographic symmetrical multiprocessing systems. The method is recommended for routine control of finished and semi-finished pharmaceutical preparations containing from 25 to 200 mg/ml of enoxaparin sodium-containing.Conclusion. The proposed method can be used for routine quality control of enoxaparin sodium-containing preparations for injection.

A Strategy for Developing an Effective Cache Catalogue in the Communication Domain

This research paper presents a method and device for resolving the challenges faced in the prior art, specifically related to low access speed of the cache catalogue and low storage use efficiency. The proposed method involves the construction of a cache catalogue, comprising a public data catalogue and a private data catalogue. The public data catalogue records data block information of public data, while the private data catalogue records data block information of private data. Additionally, the method includes determining the data type of the target data associated with a read-write request transmitted by a first processor. This data type can be classified as private data or public data. The target data's data block information is then recorded in the cache catalogue. The method and device presented in this research are suitable for the communication field and aim to enhance the recording of data block information in a multi-processor system.

Axial multi-focus stealth cutting method based on the fractional Fourier transform for quartz glass

Aiming at the problems of quality defects, low efficiency, and insufficient flexibility in the traditional glass cutting process, this paper proposes a holographic ultrafast laser axial multi-focus stealth cutting method. By changing the fractional Fourier transform order, combined with the 3D-GSW iterative optimization algorithm, the spatial position and energy of the axial multi-focus can be flexibly adjusted. Focusing the axial multi-focus inside the quartz glass not only improves cutting efficiency but also eliminates the defects such as chipping and microcracks. This processing method has good prospects for applications in optical material processing and optical manipulation. A holographic ultrafast laser parallel processing system was built, and the diffraction efficiency and light intensity uniformity of the axial multi-focus were simulated and analyzed. Using this stealth cutting method, a single scanning cutting of quartz glass (200 μm) was successfully achieved with intact glass edges and no microcracks. The minimum roughness of the cutting section is 2.21 μm.

Component connectivity of augmented cubes

Classical connectivity is a vital metric to explore fault tolerance and reliability of network-based multiprocessor systems. The component connectivity is a more advanced metric to assess the fault tolerance of network structures beyond connectivity and has gained great progress. For a non-complete graph G=(V(G),E(G)), a subset T⊆V(G) is called an r-component cut of G, if G−T is disconnected and has at least r components (r≥2). The r-component connectivity of G, denoted by cκr(G), is the cardinality of the minimum r-component cut. The component connectivities of some networks for small r have been determined, while some progresses for large r only focus on the networks which take hypercube as their modules. In this paper, we determine the (r+1)-component connectivity of augmented cubes cκr+1(AQn)=2nr−4r−(r2)+3, for n≥13, 6≤r≤⌊n−12⌋, and particularly cκr+1(AQn)=2nr−4r−(r2)+2 for n≥5, r∈{4,5}.

An O(log(N)) Algorithm View: Reliability Evaluation of Folded-crossed Hypercube in Terms of h-extra Edge-connectivity

An interconnection network can be modelled as a connected graph [Formula: see text]. The reliability of interconnection networks is critical for multiprocessor systems. Several conditional edge-connectivities have been introduced in the past for accurately reflecting various realistic network situations, with the [Formula: see text]-extra edge-connectivity being one such conditional edge-connectivity. The [Formula: see text]-extra edge-connectivity of [Formula: see text], denoted by [Formula: see text], is the minimum cardinality of faulty edges whose deletion disconnects the graph [Formula: see text] with each resulting component containing at least [Formula: see text] processors. In general, for a connected graph [Formula: see text], determining whether the graph exists an [Formula: see text]-extra edge-cut is [Formula: see text]-hard. The folded-crossed hypercube [Formula: see text] is a variation of the crossed hypercube [Formula: see text] with [Formula: see text] processors. In this paper, after excavating the layer structure of folded-crossed hypercube, we investigate some recursive properties of [Formula: see text], based on some recursive properties, an effective [Formula: see text] algorithm of [Formula: see text]-extra edge-connectivity of folded-crossed hypercube is designed, which can determine the exact value and the [Formula: see text]-optimality of [Formula: see text] for each positive integer [Formula: see text]. Our results solve this problem thoroughly.

A Reliability System Evaluation Model of NoC Communication with Crosstalk Analysis from Backend to Frontend

Network on chip (NoC) is the main solution to the communication bandwidth of a multi-processor system on chip (MPSoC). NoC also brings more route requirements and is highly prone to errors caused by crosstalk. Crosstalk has become a major design problem in deep-submicron NoC communication design. Hence, a crosstalk error model and corresponding reliable system with error correction code (ECC) are required to make NoC communication reliable. In this paper, a reliability system evaluation model (RSE) of NoC communication with analysis from backend to frontend has been proposed. In the backend, a crosstalk error rate model (CER) is established with a three-wire RLC coupling model and timing constraints. The CER is used to establish functional relations between interconnect spacing, length and signal frequency, and test system reliability. In the frontend, a reliability system performance model (RSP) is established with a CER, reliability method cost and bandwidth. The RSE summarizes the frontend and backend model. In order to verify the RSE model, we propose a reliability system with a hybrid automatic repeat request technique (RSHARQ). Simulation demonstrates that the CER model is close to real circuit design. Through the CER and RSP model, the performance of RSHARQ could be simulated.

Hyper star fault tolerance of bubble sort networks

Let H and M be two connected subgraphs of an interconnection network G. If the removal of any minimum H-structure-cut (resp. minimum H-substructure-cut) splits G into exactly two components, one of which is isomorphic to M, then G is said to be hyperH|M-connected (resp. hyper sub-H|M-connected). The bubble sort graph Bn is one of alternative interconnection networks for multiprocessor systems. Let n≥7 and 2≤r≤4. Denote by K1 the complete graph on one vertex and denote by K1,r a star on 1+r vertices. In this paper, we prove that (i) both the K1,r-structure connectivity and the sub-K1,r-structure connectivity of Bn are ⌈n−12⌉; and (ii)Bn is hyper K1,r|K1-connected and hyper sub-K1,r|K1-connected.

Cars logo recognition by using of backpropagation neural networks

Numerous developments in creating “intelligent” programs have been made, some of which have drawn inspiration from biological neural networks. Researchers are developing artificial neural networks (ANNs) from various scientific fields to address multiple issues in prediction, control, and optimization. Many s, densely connected processors make up artificial neural networks, which can be considered parallel and distributed processing systems. This paper uses a back propagation ANN algorithm to recognize cars' logos. Sixty-eight images are used, which represents the logo of vehicles and their distortion and rotation, to simulate human eye recognition. The proposed design is trained by using a supervised learning algorithm. The designed system successfully validates the car logos by 99.6%, which consider a high percentage in such a field. Finally, the implemented system presents a real-life application of ANN.

Hyper Star Fault Tolerance of Hierarchical Star Networks

Let [Formula: see text] and [Formula: see text] be two connected subgraphs of an interconnection network [Formula: see text]. If the removal of any minimum [Formula: see text]-structure-cut (respectively, minimum [Formula: see text]-substructure-cut) splits [Formula: see text] into exactly two components, one of which is isomorphic to [Formula: see text], then [Formula: see text] is said to be hyper[Formula: see text]-connected (respectively, hyper sub-[Formula: see text]-connected). The hierarchical star network [Formula: see text] is one of alternative interconnection networks for multiprocessor systems. Let [Formula: see text], [Formula: see text] and [Formula: see text]. In this paper, we prove that (i) both the [Formula: see text]-structure connectivity and the sub-[Formula: see text]-structure connectivity of [Formula: see text] are [Formula: see text]; and (ii) both the [Formula: see text]-structure connectivity and the sub-[Formula: see text]-structure connectivity of [Formula: see text] are [Formula: see text]; and (iii) [Formula: see text] is hyper [Formula: see text]-connected and hyper sub-[Formula: see text]-connected, where [Formula: see text] is the complete graph with one vertex and [Formula: see text] is a star with [Formula: see text] vertices.

Optical-electronic hybrid Fourier convolutional neural network based on super-pixel complex-valued modulation.

An optical-electronic hybrid convolutional neural network (CNN) system is proposed and investigated for its parallel processing capability and system design robustness. It is regarded as a practical way to implement real-time optical computing. In this paper, we propose a complex-valued modulation method based on an amplitude-only liquid-crystal-on-silicon spatial light modulator and a fixed four-level diffractive optical element. A comparison of computational results of convolutions between different modulation methods in the Fourier plane shows the feasibility of the proposed complex-valued modulation method. A hybrid CNN model with one convolutional layer of multiple channels is proposed and trained electrically for different classification tasks. Our simulation results show that this model has a classification accuracy of 97.55% for MNIST, 88.81% for Fashion MNIST, and 56.16% for Cifar10, which outperforms models using only amplitude or phase modulation and is comparable to the ideal complex-valued modulation method.

The generalized measure of edge fault tolerance in exchanged 3-ary n-cube

The exchanged 3-ary n-cube , proposed by Lv et al. in 2021, is obtained by removing edges from a 3-ary n-cube , where r + s + t + 1 = n. The topological interconnection network of a multiprocessor system can be modeled as a connected graph. Analyzing the fault tolerance of its topological structure is critical in the course of design and maintenance of it. Given a connected graph G, let F be an edge subset of G. F is called an h-edge-cut of G, if G−F is disconnected and each remaining component has the minimum degree of at least h. The h-edge-connectivity is the minimum cardinality of all h-edge-cuts of G. For and , in this paper, we determine the -edge-connectivity of exchanged 3-ary n-cubes, , and prove the exact values .

A Novel Approach for Integrated Shortest Path Finding Algorithm (ISPSA) Using Mesh Topologies and Networks-on-Chip (NOC)

A novel data dispatching or communication technique based on circulating networks of any network IP is suggested for multi data transmission in multiprocessor systems using Networks-On-Chip (NoC). In wireless communication network management have some negatives have heavy data losses and traffic of data sending data while packet scheduling and low performance in the varied network due to workloads. To overcome the drawbacks, in this method proposed system is Integrated Shortest Path Search Algorithm (ISPSA) using mesh topologies. The message is sent to IP (Internet Protocol) in the network until the specified bus accepts it. Integrated Shortest Path Search Algorithm for communication between two nodes is possible at any one moment. On-chip wireless communications operating at specific frequencies are the most capable option for overcoming metal interconnects multi-hop delay and excessive power consumption in Network-on-Chip (NoC) devices. Each node can be indicated by a pair of coordinates (level, position), where the level is the tree's vertical level and the view point is its horizontal arrangement in the sequence of left to right. The output gateway node's n nodes are linked to two nodes in the following level, with all resource nodes located at the bottommost vertical level and the constraint of this topology is its narrow bisection area. The software Xilinx 14.5 tool by using that overall performance analysis of mesh topology, each method are reduced data losses with better accuracy although the productivity of the delay is decreased by 21 % was evaluated and calculated..

Imitation Learning-Based Performance-Power Trade-Off Uncore Frequency Scaling Policy for Multicore System.

As the importance of uncore components, such as shared cache slices and memory controllers, increases in processor architecture, the percentage of uncore power consumption in the overall power consumption of multicore processors rises significantly. To maximize the power efficiency of a multicore processor system, we investigate the uncore frequency scaling (UFS) policy and propose a novel imitation learning-based uncore frequency control policy. This policy performs online learning based on the DAgger algorithm and converts the annotation cost of online aggregation data into fine-tuning of the expert model. This design optimizes the online learning efficiency and improves the generality of the UFS policy on unseen loads. On the other hand, we shift our policy optimization target to Performance Per Watt (PPW), i.e., the power efficiency of the processor, to avoid saving a percentage of power while losing a larger percentage of performance. The experimental results show that our proposed policy outperforms the current advanced UFS policy in the benchmark test sequence of SPEC CPU2017. Our policy has a maximum improvement of about 10% relative to the performance-first policies. In the unseen processor load, the tuning decision made by our policy after collecting 50 aggregation data can maintain the processor stably near the optimal power efficiency state.

Organization of Calculations and Work with Memory in the Educational Programming Language SYNHRO

The article is devoted to a number of decisions made in the project of the educational programming language Synchro, which is being developed at the Laboratory of Information Systems of the A.P. Ershov IIS SB RAS, designed to familiarize with the basic phenomena of the interaction of processes and control of calculations over shared memory. The focus is on the functional programming paradigm. The language is aimed at schoolchildren of primary and secondary grades, as well as junior students and non-professionals. During training, the experience of operating with toy robots moving on a checkered board is used. The article is of interest to everyone who is interested in the problems of modern computer science, programming and information technology, especially the problems of parallel computing on supercomputers and distributed systems, and in general the use of multiprocessor systems.

Design and Performance Analysis of Low Latency Routing Algorithm based NoC for MPSoC

The Network on Chip is appropriate where System-on-Chip technology is scalable and adaptable. The Network on Chip is a new communication architecture with a number of benefits, including scalability, flexibility, and reusability, for applications built on Multiprocessor System on a Chip (MPSoC). However, the design of efficient NoC fabric with high performance is critically complex because of its architectural parameters. Identifying a suitable scheduling algorithm to resolve arbitration among ports to obtain high-speed data transfer in the router is one of the most significant phases while designing a Network on chip based Multiprocessor System on a Chip. Low latency, throughput, space utilization, energy consumption, and reliability for Network on chip fabric are all determined by the router. The performance of the NoC system is hampered by the deadlock issues that plague conventional routing algorithms. This work develops a novel routing algorithm to address the deadlock problem. In this paper, a deterministic shortest path deadlock-free routing method is developed based on the analysis of the Turn Model. In the 2D-mesh structure, the algorithm uses separate routing methods for the odd and even columns. This minimizes the number of paths for a single channel, congestion, and latency. Two test scenarios—one with and one without a load test—were used to evaluate the proposed model. For a zero-load network, three clock cycles are utilized to transfer the packets. For the load network, five clocks are utilized to transfer the packets. The latency is measured for both cases without load and with load test and the corresponding latency is 3ns and 7ns respectively.The proposed method has an 18.57Mbps throughput. The area and power utilization for the proposed method are 69% (IO utilization) and 0.128W respectively. In order to validate the proposed method, the latency is compared with existing work and 50% latency is reduced both with and without congestion load.

An Optimal DPM Based Energy-Aware Task Scheduling for Performance Enhancement in Embedded MPSoC

Minimizing the energy consumption to increase the life span and performance of multiprocessor system on chip (MPSoC) has become an integral chip design issue for multiprocessor systems. The performance measurement of computational systems is changing with the advancement in technology. Due to shrinking and smaller chip size power densities on-chip are increasing rapidly that increasing chip temperature in multi-core embedded technologies. The operating speed of the device decreases when power consumption reaches a threshold that causes a delay in complementary metal oxide semiconductor (CMOS) circuits because high on-chip temperature adversely affects the life span of the chip. In this paper an energy-aware dynamic power management technique based on energy aware earliest deadline first (EA-EDF) scheduling is proposed for improving the performance and reliability by reducing energy and power consumption in the system on chip (SOC). Dynamic power management (DPM) enables MPSOC to reduce power and energy consumption by adopting a suitable core configuration for task migration. Task migration avoids peak temperature values in the multi-core system. High utilization factor ( on central processing unit (CPU) core consumes more energy and increases the temperature on-chip. Our technique switches the core by migrating such task to a core that has less temperature and is in a low power state. The proposed EA-EDF scheduling technique migrates load on different cores to attain stability in temperature among multiple cores of the CPU and optimized the duration of the idle and sleep periods to enable the low-temperature core. The effectiveness of the EA-EDF approach reduces the utilization and energy consumption compared to other existing methods and works. The simulation results show the improvement in performance by optimizing 4.8% on 9%, 16%, 23% and 25% at 520 MHz operating frequency as compared to other energy-aware techniques for MPSoCs when the least number of tasks is in running state and can schedule more tasks to make an energy-efficient processor by controlling and managing the energy consumption of MPSoC.

FULL ENUMERATION METHODS ON GRAPHS

Requirements for algorithms for specific problems of discrete mathematics are changing. This is dictated by an urgent need to increase calculation accuracy in technology-related problems brought about by rapid digitization and virtualization, which actively permeated various scientific areas and changes the approach to previously studied objects. These objects include n-dimensional structures, known as circular structures, that describe global processes occurring in communication networks, multi-processor systems, in collective communications, stock market structures etc. Given that, both the development of new mathematical methods of solving problems and the solution of related calculation problems are deemed important. The enumeration method, based on various modifications of systematic viewing (traversal) of graph elements and labeling, has been widely used and quite fully developed for a long time. The purpose of the article is to announce graphs presentation and the enumeration methods on graphs presentations: the transposition method and the node-graph method. This publication presents the basic results of the author's work on reducing the severity of the NP-complete problem class.

Energy-Efficient Scheduling Based on Task Migration Policy Using DPM for燞omogeneous MPSoCs

Increasing the life span and efficiency of Multiprocessor System on Chip (MPSoC) by reducing power and energy utilization has become a critical chip design challenge for multiprocessor systems. With the advancement of technology, the performance management of central processing unit (CPU) is changing. Power densities and thermal effects are quickly increasing in multi-core embedded technologies due to shrinking of chip size. When energy consumption reaches a threshold that creates a delay in complementary metal oxide semiconductor (CMOS) circuits and reduces the speed by 10%–15% because excessive on-chip temperature shortens the chip’s life cycle. In this paper, we address the scheduling & energy utilization problem by introducing and evaluating an optimal energy-aware earliest deadline first scheduling (EA-EDF) based technique for multiprocessor environments with task migration that enhances the performance and efficiency in multiprocessor system-on-chip while lowering energy and power consumption. The selection of core and migration of tasks prevents the system from reaching its maximum energy utilization while effectively using the dynamic power management (DPM) policy. Increase in the execution of tasks the temperature and utilization factor on-chip increases that dissipate more power. The proposed approach migrates such tasks to the core that produces less heat and consumes less power by distributing the load on other cores to lower the temperature and optimizes the duration of idle and sleep times across multiple CPUs. The performance of the EA-EDF algorithm was evaluated by an extensive set of experiments, where excellent results were reported when compared to other current techniques, the efficacy of the proposed methodology reduces the power and energy consumption by 4.3%–4.7% on a utilization of 6%, 36% & 46% at 520 & 624 MHz operating frequency when particularly in comparison to other energy-aware methods for MPSoCs. Tasks are running and accurately scheduled to make an energy-efficient processor by controlling and managing the thermal effects on-chip and optimizing the energy consumption of MPSoCs.

MPSoC design and implementation using microblaze soft core processor architecture for faster execution of arithmetic application

The research paper presents the design methodology with novel task distribution technique on multi-processor system on chip (MPSoC) for speeding up the execution of arithmetic application. Utilisation of multiple soft core processors on field programmable gate array (FPGA) reduces the overload of adding external hardware to a system. Parallel processing of soft core processor with proposed task distribution technique makes any application to execute at faster rate. This task distribution based speed enhancement technique for arithmetic application is very feasible and appealing to the modern applications like neural networks, fuzzy logic, algorithms of machine learning etc. Experimentation on such architecture with arithmetic application shows significant increase in speed of operation with respect to conventional design. This is implemented using Microblaze soft core processor architecture on Xilinx Virtex 5 FPGA board.

Влияние концевого вихря крыла-генератора на обтекание основного крыла под углом атаки

The effect of a tip vortex from an upstream generator wing on the flow around the main wing in a supersonic flow is considered. Numerical results were obtained on the multiprocessor hybrid supercomputer system K-60 at the Keldysh Institute of Applied Mathematics RAS.