Multiply Operations Research Articles

Neural networks

We've all heard a proselytizing hyperbolist make the artificial-intelligence-is-going-to-steal-my-job speech. If you subscribe, look at the code in the notebook accompanying this tutorial at https://github.com/seg/tutorials-2018 . It demonstrates a small neural network. You'll find a simple system composed chiefly of multiply and add operations. That's really all that happens inside a neural network. Multiply and add. There's no magic here.

Design and implementation of GPS baseband correlator

Correlator design is the core part of the GPS baseband processor design. In this paper, the idea of the modular is used to design the local NCO, pseudo-code generator, mixer, integral-clear filter, phase detector and loop filter. Each module is completed by Verilog and validated on the FPGA. An alternative true value operation is ultilized on the mixer to replace the multiplier operation of the input signal in this paper, thereby reducing the computational complexity. By initializing G2 register of the PN generator, it can remove the design of the phase selector. FPGA verification results show that the improved GPS baseband correlator can reduce resource consumption, accelerate the processing speed, and correctly demodulate the navigation data from input GPS signals.

A Low-Power Frequency Multiplier for Multi-GHz Applications

A programmable frequency multiplier operating in GHz frequency range is proposed in this paper. The architecture is based on the combination of a multi-segment programmable and power efficient phase interpolator with an edge combiner. The system is designed in a 65 nm process with 1.0 V supply voltage offering a multiplication factor ranging from 1 to 8 with integer step. The layout area is 104 μm × 96 μm and the power consumption is 6.6 mW for 4.992 GHz output frequency. Post-layout simulation results including the multi-phase ring oscillator verify −91.6 dBc/Hz phase noise at 4.992 GHz for 1 MHz frequency offset.

New efficient identity based encryption without pairings

Identity based encryption (IBE) schemes were first constructed with, and often have been since, bilinear mappings (a.k.a. pairings) on elliptic curves. But the multiply and exponent operation using pairings is slowly and inefficiency in implementation. There were, however, some successful attempts to construct IBE schemes based on more traditional number theoretic problems. Unfortunately, most of the proposed schemes are impractical as a result of bandwidth utilization or the time complexity of performance. By this work, we present a new efficient IBE scheme without pairings, which is inspired from the trapdoor technique rooted in composite residuosity class problem. Firstly, our converted basic IBE scheme is proven, in the random oracle model, secure against chosen-plaintext attacks (CPA) under the assumptions that the decision composite residuosity and decision partial discrete logarithm problems are intractable. Moreover, we employ the technique of Fujisaki–Okamoto to transform the basic scheme into enhanced one for resisting chosen-ciphertext attacks (CCA).

Performance evolution of 4-b bit MAC unit using hybrid GDI and transmission gate based adder and multiplier circuits in 180 and 90 nm technology

This paper presents the high-speed adder circuit design based on 18 transistor (18T) full swing gate diffusion input based logic gates and transmission based techniques to compute the sum and carry bits, respectively. The proposed adder logic operates at 1.8 and 1.2 V supply voltage. The 180 and 90 nm technology are used for the proposed architectures. The proposed design consists of less power delay products and reduces 28.57% as compared to conventional 16 transistor based adder cells. The proposed adder circuit increases the transistor count by a factor of 2. The performance of the proposed 1-bit adder circuit is testified to design 4-bit ripple carry, carry save and carry select adder circuits, with reduced circuit parameters in terms of power, delay and power delay products. In addition, the performance of the proposed adder circuit are checked to design Barun and Baugh Wooley multipliers. Finally, the low power and high-speed MAC unit is designed with the proposed adder, multiplier and register circuits. The proposed MAC unit achieves significant improvements in power-delay product as compared to conventional designs. The proposed adder, multiplier and MAC unit operation is performed wih the number of samples using Monte Carlo simulation tool. The performance evolution of the circuit parameters including power, delay and power-delay products are verified using the Cadence software Virtuoso software.

PENGGUNAAN MODEL PEMBELAJARAN KOOPERATIF TIPE STUDENT TEAMS ACHIEVEMENT DIVISION (STAD) UNTUK MENINGKATKAN PEMAHAMAN KONSEP MATERI OPERASI HITUNG PERKALIAN PADA SISWA KELAS IV

This research is based on the low understanding of the concept of Mathematics students in learning Mathematics material of multiplication operation in SD Negeri Nugraha Pelita. The problem is caused by the learning process that is still using conventional methods. This makes learning tends to be boring and students find it difficult to understand the learning materials that have been delivered, so that the impact of student understanding is likely to be low. Student Teams Achievement Division (STAD) cooperative learning model is very effective to be used as solution to solve the learning problem that happened during this time. The method used in this research is PTK method (Classroom Action Research). The subject of this research is the fourth grade students of SD Negeri Nugraha Pelita in the academic year 2017/2018 with the number of 33 people. Based on the results of learning and research analysis it can be concluded that the model of cooperative learning type Student Teams Achievement Division (STAD) can improve students' learning comprehension on Mathematics subjects of multiply counting operations in the fourth grade of SD Negeri Nugraha Pelita.

An efficient subarray average delay multiply and sum beamformer algorithm in ultrasound imaging

Beamformer plays an important role in medical ultrasound imaging systems. The delay multiply and sum (DMAS) beamformer achieves better performance in contrast and resolution compared with the delay and sum (DAS) beamformer, but suffers from higher computational complexity and partial energy loss. The higher computational complexity mainly arises from the multiply and geometric average operation, which needs (N2-N)/2 computations at every point, where N denotes the number of array elements. The partial energy loss, mainly due to the autocorrelation component of the echo signals, has been neglected in the DMAS beamformer. In this paper, we propose a subarray average delay multiply and sum (SA-DMAS) beamformer which is combined with subarray average technique of covariance matrix and DMAS beamformer. This will lower the computational complexity, while keeping the side lobe suppressing property of DMAS. The main idea of the proposed method is adding autocorrelation component of the echo signals to DMAS, and converting the expression in covariance matrix form. The subarray average technique is used to estimate the covariance matrix of the echo signals. The field II simulation of point targets and cyst phantoms was used to prove the performance of the proposed method. An RF data experiment was applied to support the feasibility and validity of our method. The simulation and experimental results show that our method has a lower computational complexity as O(9/2L2) , where L denotes the sub-array size, and has equivalent performance like the MV and DMAS beamformer.

A Resource-Limited Hardware Accelerator for Convolutional Neural Networks in Embedded Vision Applications

In this brief, we introduce an architecture for accelerating convolution stages in convolutional neural networks (CNNs) implemented in embedded vision systems. The purpose of the architecture is to exploit the inherent parallelism in CNNs to reduce the required bandwidth, resource usage, and power consumption of highly computationally complex convolution operations as required by real-time embedded applications. We also implement the proposed architecture using fixed-point arithmetic on a ZC706 evaluation board that features a Xilinx Zynq-7000 system on-chip, where the embedded ARM processor with high clocking speed is used as the main controller to increase the flexibility and speed. The proposed architecture runs under a frequency of 150 MHz, which leads to 19.2 Giga multiply accumulation operations per second while consuming less than 10 W in power. This is done using only 391 DSP48 modules, which shows significant utilization improvement compared to the state-of-the-art architectures.

CO2 operation of an active target detector readout based on THGEM.

We present and discuss a systematic study of the operation of THick Gaseous Electron Multipliers (THGEM)-like structures in pure CO2, in view of possible applications as Active Target Time Projection Chambers (AT-TPC) readout. The ultimate goal is to use oxygen-rich gas as active medium to perform nuclear physics/astrophysics experiments on stable oxygen isotopes (16O,17O,18O). We report the measurement of the effective avalanche gain of ceramic Multi-layer THGEMs (M-THGEMs), for different geometries (two- and three-layers M-THGEM) at various pressures. In addition, we report the analysis of the tracking performance of a large-volume AT-TPC equipped with a position-sensitive MICROMEGAS detector and double-cascade THGEMs pre-amplification stage. The AT-TPC was irradiated with 6.1 MeV α-particles from a 252Cf source mounted inside the detector vessel, filled with pure CO2 at 50 torr. High gain operation was achieved in CO2 at relative low pressure (0< 15 torr), of interest for AT-TPC experiments. For higher pressure the operation of the detector became unstable. The maximum achievable gain decreased to lower value—below 103 at 450 torr. Through the image analysis of the α-particle tracks we computed an energy resolution of around 3% (FWHM) based on the α-particle range, while the energy resolution from the collected charge is around 5% (FWHM).

Quantum realization of the bilinear interpolation method for NEQR

In recent years, quantum image processing is one of the most active fields in quantum computation and quantum information. Image scaling as a kind of image geometric transformation has been widely studied and applied in the classical image processing, however, the quantum version of which does not exist. This paper is concerned with the feasibility of the classical bilinear interpolation based on novel enhanced quantum image representation (NEQR). Firstly, the feasibility of the bilinear interpolation for NEQR is proven. Then the concrete quantum circuits of the bilinear interpolation including scaling up and scaling down for NEQR are given by using the multiply Control-Not operation, special adding one operation, the reverse parallel adder, parallel subtractor, multiplier and division operations. Finally, the complexity analysis of the quantum network circuit based on the basic quantum gates is deduced. Simulation result shows that the scaled-up image using bilinear interpolation is clearer and less distorted than nearest interpolation.

Comparative analysis of fourth-harmonic multiplying gyrotron traveling-wave amplifiers operating at different frequency multiplications

The harmonic multiplying operation in a gyrotron traveling-wave amplifier (gyro-TWA) permits magnetic field reduction and frequency multiplication. This study presents a comparative analysis of fourth-harmonic multiplying gyro-TWAs with three schemes of operation. An improved mode-selective circuit using circular waveguides with various radii provides the rejection points within the range of operating frequencies to suppress the competing modes of gyro-TWAs. The simulated results reveal that gyro-TWAs are the most susceptible to the fundamental-harmonic TE11 competing mode, regardless of the operating scheme, and that the mode-selective circuit can provide an attenuation of more than 20 dB to suppress the competing modes. The amplification of the waves in a gyro-TWA depends on the lengths of the sections, and the simulated results show that the gain increases for all schemes, as the length of the lossy section or the length of the copper section increases. All schemes exhibit nearly the same saturated output powers and bandwidths; however, the saturated gain of the scheme at a high frequency multiplication ratio is less than that of the scheme at a low frequency multiplication ratio. Extensive numerical calculations of power and gain scaling are conducted for all schemes.

Accelerating Real-Time Time-Dependent Density Functional Theory with a Nonrecursive Chebyshev Expansion of the Quantum Propagator.

Solutions of the real-time time-dependent density functional theory (RT-TDDFT) equations provide an affordable route to understanding the electronic dynamics that underpins many spectroscopic techniques. From the solutions of the RT-TDDFT equations, it is possible to extract optical absorption and circular dichroism spectra, as well as descriptions of charge transfer and charge transport dynamics. In order to apply RT-TDDFT to increasingly large systems, it is necessary to develop methods to overcome computational bottlenecks. One current bottleneck is the [Formula: see text] cost required to form the time propagator for the RT-TDDFT equations, because of the full matrix diagonalization that is required at each time step. Here, we present a (semi)diagonalization-free formation of the propagator based on a nonrecursive Chebyshev polynomial expansion. The Chebyshev expansion relies only on matrix multiply operations which have lower computational cost and are furthermore extremely parallelizable. We demonstrate the accuracy and stability of the Chebyshev approach, and then discuss the favorable scaling of the method, compared to traditional approaches based on matrix diagonalization. The Chebyshev expansion method should enable the application of RT-TDDFT methods to large systems such as nanocrystals and biomolecules.

A simple spatial domain algorithm to increase the residues of wrapped phase maps

In phase unwrapping, the locations and densities of the residues are indicative of the severity of the unwrapping problem. Gdeisat et al. proposed an algorithm to increase the number of residues in a wrapped phase map to improve the results of phase unwrapping. The method proposed, though, is extremely time-consuming involving the computation of a Fourier transform along with the selection and shift of its spectral components. Moreover, there is no theoretical analysis on the reasons why the frequency shift should be able to increase the number of residues. In an attempt to address these problems, we propose a simple algorithm to increase the number of residues in a wrapped phase map. The algorithm uses a simple multiply operation in spatial domain to realize the frequency shift exploiting the frequency shift property of Fourier transform. We also discuss the relationship between the number of residues and frequency shift. Experimental results have demonstrated that the proposed method can speed up by more than 50% of the calculation time.

Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation

Fast Fourier transform (FFT) coprocessor, having a significant impact on the performance of communication systems, has been a hot topic of research for many years. The FFT function consists of consecutive multiply add operations over complex numbers, dubbed as butterfly units. Applying floating-point (FP) arithmetic to FFT architectures, specifically butterfly units, has become more popular recently. It offloads compute-intensive tasks from general-purpose processors by dismissing FP concerns (e.g., scaling and overflow/underflow). However, the major downside of FP butterfly is its slowness in comparison with its fixed-point counterpart. This reveals the incentive to develop a high-speed FP butterfly architecture to mitigate FP slowness. This brief proposes a fast FP butterfly unit using a devised FP fused-dot-product-add (FDPA) unit, to compute AB ± CD ± E, based on binary-signed-digit (BSD) representation. The FP three-operand BSD adder and the FP BSD constant multiplier are the constituents of the proposed FDPA unit. A carry-limited BSD adder is proposed and used in the three-operand adder and the parallel BSD multiplier so as to improve the speed of the FDPA unit. Moreover, modified Booth encoding is used to accelerate the BSD multiplier. The synthesis results show that the proposed FP butterfly architecture is much faster than previous counterparts but at the cost of more area.

Low-voltage harmonic multiplying gyrotron traveling-wave amplifier in G band

Harmonic multiplying operation in a gyrotron traveling-wave amplifier (gyro-TWA) permits for magnetic field reduction and frequency multiplication. Lowering a beam voltage is an important step toward miniaturization of a harmonic multiplying gyro-TWA. However, the additional degree of freedom that is provided by the multitude cyclotron harmonics in a low-voltage harmonic multiplying gyro-TWA still easily generates various competing modes. An improved mode-selective circuit, using circular waveguides with various radii, can provide the rejection points within the frequency range to suppress competing modes. Simulated results reveal that the mode-selective circuit can provide an attenuation of more than 14 dB to suppress the competing modes. Furthermore, the performance of the gyro-TWA is analyzed for studying the sensitivity of the saturated output power and full width at half maximum bandwidth of the gyro-TWA to the beam voltage and the magnetic field. A stable low-voltage harmonic multiplying gyro-TWA with the mode-selective circuit is predicted to yield a peak output power of 24 kW at 200.4 GHz, corresponding to a saturated gain of 56 dB at an interaction efficiency of 20%. The full width at half maximum bandwidth is 3.0 GHz.

Continuous Monitoring of Formaldehyde Photolysis Products by THz Spectroscopy

A terahertz sensor system based on a commercially available multiplier chain operating in the range 600–900 GHz is used to monitor the photolysis of formaldehyde H2CO. The exposure of formaldehyde to solar radiation provokes dissociation via two pathways: 1) the molecular channel producing molecular carbon monoxide CO and 2) the radicalar channel giving formyl HCO. Monitoring the concentrations of CO and H2CO via pure rotational transitions, allowed us to obtain the kinetic rate constants for these two channels. In order to establish the detection limit of HCO, a modified spectrometer configuration employing the Zeeman modulation was used with acetaldehyde CH3CHO and photosensitization by mercury.

IJARCCE - Computer and Communication Engineering

2 Abstract: A new architecture namely 2-D DWT, Multiplier-and accumulator (MAC) based Radix-4 Booth Multiplication Algorithm for high-speed arithmetic logics have been proposed and implemented on Xilinx. By combining multiplication with accumulation and devising a hybrid type adder the performance was improved. The modified booth encoder will reduce the number of partial products generated by a factor of 2. Fast multipliers are essential parts of digital signal processing systems. The speed of multiply operation is of great importance in digital signal processing as well as in the general purpose processors. The number to be added is the multiplicand, the number of times that it is added is the multiplier, and the result is the product. Each step of addition generates a partial product. the simulation is done on the Modelsim and finally output is analysed by using Matlab.

Two-Switch Voltage Equalizer Using a Series-Resonant Voltage Multiplier Operating in Frequency-Multiplied Discontinuous Conduction Mode for Series-Connected Supercapacitors

Two-Switch Voltage Equalizer Using a Series-Resonant Voltage Multiplier Operating in Frequency-Multiplied Discontinuous Conduction Mode for Series-Connected Supercapacitors

IJIREEICE - Electrical, Electronics, Instrumentation and Control

A new architecture, namely, Multiplier-and accumulator (MAC) based Radix-4 Booth Multiplication Algorithm for high-speed arithmetic logics have been proposed and implemented on Xilinx FPGA device. By combining multiplication with accumulation and devising a hybrid type adder the performance was improved. The modified booth encoder will reduce the number of partial products generated by a factor of 2. Fast multipliers are essential parts of digital signal processing systems. The speed of multiply operation is of great importance in digital signal processing as well as in the general purpose processors. The number to be added is the multiplicand, the number of times that it is added is the multiplier, and the result is the product. Each step of addition generates a partial product.

A hardware–software co-design approach for implementing sparse matrix vector multiplication on FPGAs

The Field-Programmable Gate Array is an excellent match for the Sparse Matrix–Vector Multiply (SMVM) operation because of its enormous computational capacity and its ability to build a custom memory hierarchy that matches the memory access patterns of the operation. This paper describes a new sparse matrix storage format which works in conjunction with a custom memory subsystem which decodes the format on-the-fly. The SMVM operation is implemented on a single FPGA and a small parallel system of four FPGAs. The parameters that affect the performance of the sequential and parallel designs are investigated as well as the speedup for different matrices.