Abstract
A programmable frequency multiplier operating in GHz frequency range is proposed in this paper. The architecture is based on the combination of a multi-segment programmable and power efficient phase interpolator with an edge combiner. The system is designed in a 65 nm process with 1.0 V supply voltage offering a multiplication factor ranging from 1 to 8 with integer step. The layout area is 104 μm × 96 μm and the power consumption is 6.6 mW for 4.992 GHz output frequency. Post-layout simulation results including the multi-phase ring oscillator verify −91.6 dBc/Hz phase noise at 4.992 GHz for 1 MHz frequency offset.
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