Multiplierless Filters Research Articles

Design of reconfigurable multiplier-less filter structure based on IFIR for digital channelizer

The flexibility in frequency allocation is essential for high throughput satellites (HTS). The digital channelizer based transponder system has a crucial role in enhancing the performance of HTS. In this work, the design and implementation of a low computational complexity digital channelizer for HTS is proposed. The proposed reconfigurable filter structure for digital channelizer is to generate non-uniform and sharp transition width FIR filters for transponder of the satellite systems. The multipliers and group delay needed in the digital channelizer that employ the proposed structure are reduced when compared to FRM and traditional IFIR based digital channelizer. An example is used to illustrate the effectiveness of the proposed design. Results reveal that the proposed structure has a lower multiplier complexity than existing techniques. The proposed structure once implemented effectively, the power dissipation and hardware complexity are reduced. With the help of CSD, MOABC, and SIDC-CSE optimization, the filters used in this structure are made multiplier-less. Hence this structure is adaptable for the digital channelizer in the transponder of the satellite communication systems.

A Low-Complexity Multiplier-Less Filter Bank Based on Modified IFIR for the SDR Channelizer

Digital filter banks are extensively used in an SDR channelizer for channelization. The objective of this research work is to design a low computational complexity FIR filter bank for generating sharp transition width channels for SDR. The design of unified and variable bandwidth channels for SDR using the proposed structure is based on the modified IFIR filter structure and cosine modulation technique (CMT). The performance of the proposed structure is demonstrated with the help of an example. The results show that the multiplier complexity of the proposed structure is less than those of other state-of-the art methods. The optimization techniques are incorporated in this work to further reduce the complexity of the proposed structure. With the help of canonical signed digit (CSD), multi-objective artificial bee colony (MOABC) and shift inclusive differential coefficients (SIDC) – common sub-expression elimination (CSE) optimization, the filter used in this structure is made multiplier-less.

Comb decimator design based on symmetric polynomials with roots on the unit circle: Two‐stage multiplierless design and improved magnitude characteristic

AbstractThis paper presents a theoretical background for design of comb decimator based on theorem of symmetric polynomials with roots on the unit circle. A simple multiplierless filter, called zero‐separation (ZS) filter, which separates doubled comb zeros, is derived. The separation of doubled comb zeros improves comb aliasing rejection. In order to get more benefits of the ZS filter, a two‐stage structure is considered. The classic comb filters are in both stages of the proposed structure. Additionally, in the second stage, a ZS filter is inserted to improve comb aliasing rejection. The passband droop is compensated by the compensator which works at low rate and is designed using particle swarm optimization (PSO). The method is illustrated with various examples. The comparisons with methods from literature prove the benefits of the proposed work.

Performance of Multiplierless FIR Filter Based on Directed Minimal Spanning Tree: A Comparative Study

This paper presents a novel low complex configuration methodology by deploying a directed minimal spanning tree (DMST) algorithm for designing digital multiplierless finite impulse response filter. This method utilizes the shift inclusive differential coefficient and common sub-expression elimination (CSE) technique to minimize the multiple constant multiplications using steepest decent approach. The attractive feature of this work lays on the detailed comparison of the cost, reconstruction error, pass-band and stop-band error by exploiting various evolutionary techniques such as cuckoo search algorithm, particle swarm optimization, artificial bee intelligence, hybrid swarm optimization and flower pollination algorithm; followed by employing hybrid SID and DMST on these techniques. For this purpose, a mean squared error-based objective function is optimized in the pass-band and stop-band region of the filter. Further, a detailed comparison of hybrid SID and DMST with other existing CSE algorithms is also illustrated. It has been observed that up to 80% reduction in number of adders can be accomplished using the proposed DMST-based approach for multiplierless filter design.

Reducing the Cost of Implementing Filters in LoRa Devices.

This paper presents two methods to optimize LoRa (Low-Power Long-Range) devices so that implementing multiplier-less pulse shaping filters is more economical. Basic chirp waveforms can be generated more efficiently using the method of chirp segmentation so that only a quarter of the samples needs to be stored in the ROM. Quantization can also be applied to the basic chirp samples in order to reduce the number of unique input values to the filter, which in turn reduces the size of the lookup table for multiplier-less filter implementation. Various tests were performed on a simulated LoRa system in order to evaluate the impact of the quantization error on the system performance. By examining the occupied bandwidth, fast Fourier transform used for symbol demodulation, and bit-error rates, it is shown that even performing a high level of quantization does not cause significant performance degradation. Therefore, the memory requirements of LoRa devices can be significantly reduced by using the methods of chirp segmentation and quantization so as to improve the feasibility of implementing multiplier-less filters in LoRa devices.

Optimal Design of Multiplier-Less Non-uniform Channel Filters with Successive Approximation of Vectors

Applications such as software-defined radio (SDR) receivers utilize channel filters to isolate the individual frequency bands of different communication standards present in a wideband input signal. Low complexity and sharp transition width are the two important design constraints of channel filters in SDR receivers. Frequency response masking (FRM) with the multiplier-less design is an effective approach for designing sharp filters with low complexity. This paper presents an optimal design for multiplier-less implementation of FRM-based non-uniform channel filters. In the proposed design, multiplier-less channel filters are realized basing upon decomposing their impulse response values in generalized bit planes. This decomposition is based on a vector successive approximation technique in which impulse responses are successively approximated using a dictionary of vectors. The resulting coefficients of channel filters belong to signed sums of powers of two form. The proposed channel filter designs are simulated using MATLAB R2017b, and the results have been compared with the existing ones in order to signify the effectiveness of the proposed design. The simulations show that the proposed channel filter design has low complexity (number of adders) and the design time is considerably low.

A New Stochastic Inner Product Core Design for Digital FIR Filters

Stochastic computing (SC) is a computational technique with computational operations governed by probability instead of arithmetic rules. It recently found promising applications in digital and image processing areas and attracted attentions of researchers. In this paper, a new stochastic inner product (multiply and accumulate) core with an improved scaling scheme is presented for improving the accuracy and fault tolerance performance of SC based finite impulse response (FIR) digital filters. The proposed inner product core is designed using tree structured multiplexers which is capable of reducing the critical path and fault propagation in the stochastic circuitry. The designed inner product core can lead to construction of SC based light weight and multiplierless FIR digital filters. As a result, an SC based FIR digital FIR filter is implemented on Altera Cyclone V FPGA which operates on stochastic sequences of 256-bits length (8-bits precision level). Experimental results show that the developed filter has lower hardware cost, better accuracy and higher fault tolerance level compared with other stochastic implementations.

Design of multiplier-less minimum-phase filters based on sharpening compensated comb filters

Minimum-phase (MP) filters have all zeros inside and/or unit circle. As a consequence, the group delay of an MP system is always less than that of non-minimum phase systems, having the equal magnitude responses. Minimum-phase (MP) filters find applications where it is necessary to have a low group delay, like in communications, speech processing, and predictive coding, among others. This paper presents a novel simple method for the direct design of low-pass minimum-phase (MP) filters. Method is based on design of two compensated combs, using a multiplier-less minimum-phase compensator, and sharpening technique. The first comb defines the stop band and pass band of the MP filter, while the second comb decreases side lobes of the first comb, thus increasing attenuation of the resulting MP filter. Knowing that all zeros of comb filter are on the unit circle, the compensated comb is also a MP filter. Similarly, under the special condition, the sharpening of multiplier-less compensated comb may also result in a MP multiplier-less filter. The benefit of the proposed method is illustrated in the provided design examples.

FIR filters involving shifts and only two additions, efficient for short word-length signal processing

This paper investigates a class of FIR filters having a recursive multiplierless realization; the filter coefficients are conditioned in a way that, the filter architecture comprises shifts and only two additions. Besides the frequency-domain specifications, the design algorithm should also consider the input word-length to satisfy these conditions. In this paper, stochastic beam search is used as a population-based design algorithm, which internally utilizes a Branch and Bound (B&B) search to optimize its individuals. Filters Involving Shifts and Only Two Additions (ISOTA) are directly applicable on unipolar data; for bipolar data, an addition as the pre-processing and probably another as the post-processing is required. These filters have two limitations; they are efficient only for the Short Word‐Length (SWL) inputs, and the achievable frequency responses are restricted to smooth transitions. The latter problem is resolved by cascading them with other multiplierless filters such as differentiators and comb filters. The first problem seems to constrain the applications to the ΣΔ converters with coarse quantizers; but a wider application area is expected, thanks to the ΣΔ signal processing, which is based on the converting high resolution signals into higher rate SWL data. Comparative examples and a practical application are presented.

Meta-heuristic evolutionary algorithms for the design of optimal multiplier-less recombination filter banks

This paper proposes a design for multiplier-less recombination non-uniform filter banks (RNUFBs) optimized using meta-heuristic algorithms. The structure consists of an M-channel uniform filter bank, with some channels combined by the synthesis filters of a transmultiplexer (TMUX), yielding non-uniform sub-bands. When any structure is realized in hardware, it is necessary to have low power consumption and a small chip area. These can be achieved by replacing the multipliers with shifters and adders. Once the continuous coefficient recombination non-uniform filter bank is designed, the coefficients are converted to the canonic-signed-digit (CSD) space to make the design multiplier-less, so as to reduce the complexity of the hardware implementation. To reduce the number of adders and shifters in the multiplier-less implementation, the filter coefficients are rounded with a restricted number of signed power-of-two (SPT) terms, which may cause degradation in the performance of the RNUFBs. To improve the performance of the CSD rounded filters and filter bank, meta-heuristic algorithms such as the artificial bee colony (ABC) algorithm, harmony search algorithm (HSA) and gravitational search algorithm (GSA) are deployed. Of these meta-heuristic algorithms, GSA is found to give the best performance. The method proposed in this paper results in non-uniform filter banks with rational sampling factors which are multiplier-less and have linear-phase and near-perfect-reconstruction.

Framework for Digital Filter Design Optimization (DiFiDOT) using MCM Based Register Minimization Retiming for Noise Removal ECG Filters

In all the DSP(Digital Signal Processing) blocks such as digital filters, the filter coefficients are known before hand. Hence, full flexibility of the multiplier is not necessary. Multiplierless Multiple Constant Multiplication(MCM) technique can be used along with retiming for better digital filter optimization.This method is more efficient when compared to shift and add multiplications as intermediate results in MCM technique can be shared which reduces the area of multiplierless implementation of digital filters. The multiplierless filter circuit is further retimed to reduce the overall clock period which increases the clock frequency. Critical path and shortest path computations consume most of the time in retiming computation. The retiming minimizes the overall clock period by reducing the filter critical path. In the general purpose processor where actual retiming vectors are computed for digital filters, the speed with which the retiming transformation is performed suffers as the entire transformation code will be written in the form of a soft core. Hence, FPGA based path solver architecture are proposed in this paper can reduces the burden on general purpose processors while retiming. This work contributes to reduced processing time for retiming using FPGA based path solvers. Due to complexity and transistor size reduction, designing of VLSI architectures for DSP blocks has become very challenging. Automated Tools are required most often to introduce the products to market in a timely manner and to make the VLSI designs more stable, reliable and tractable. A framework called DiFiDOT(Digital Filter Design Optimization Tool) is developed in this work for synthesizing the optimized filter architectures. Finally, an application for Electrocardiography(ECG) is designed using MCM based retimed digital filters to remove the power supply interference, baseline drift and the broadband noise from the ECG signal.

Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT

The discrete wavelet transform is a fundamental block in several schemes for image compression. Its implementation relies on filters that usually require multiplications leading to a relevant hardware complexity. Distributed arithmetic is a general and effective technique to implement multiplierless filters and has been exploited in the past to implement the discrete wavelet transform as well. This work proposes a general method to implement a discrete wavelet transform architecture based on distributed arithmetic to produce approximate results. The novelty of the proposed method relies on the use of result-biasing techniques (inspired by the ones used in fixed-width multiplier architectures), which cause a very small loss of quality of the compressed image (average loss of 0.11 dB and 0.20 dB in terms of PSNR for the 9/7 and 10/18 wavelet filters, respectively). Compared with previously proposed distributed-arithmetic-based architectures for the computation of the discrete wavelet transform, this technique saves from about 20% to 25% of hardware complexity.

Design of circularly symmetric 2-D sharp wideband filters using FRM and multiplierless transformation

McClellan transformation has been established as an efficient method for synthesising two-dimensional (2-D) linear phase FIR filters. Recently, a modified McClellan transformation (T1 and T2) has been proposed which is fully multiplierless. In this paper, a design of a totally multiplierless sharp wideband circularly symmetric filter is proposed using the T1 and T2 transformations. The sharpness is achieved by designing the 1-D prototype filter using Frequency Response Masking (FRM) approach. The 1-D FRM filter is made multiplierless by designing it in the Canonic Signed Digit (CSD) space. If the 1-D multiplierless filter is mapped to the 2-D scenario using a multiplierless frequency transformation, the resulting 2-D filter is totally multipierless. The proposed design technique provides simple, fast and efficient implementation of the resulting 2-D FIR filters, with very low computational complexity compared to the traditional techniques.

Design of two-stage nonrecursive rotated comb decimation filters with droop compensation and multiplierless architecture

This paper proposes a class of decimation filters with reduced passband signal distortion and improved spurious signal rejection across the folding bands. These filters are well-suited to decimation of oversampled digital signals processed by wideband digital receivers and ΣΔ AD converters. The total decimation factor is split between two stages of decimation and zero rotation in a nonrecursive form is applied at the lower rate in order to reduce the computational complexity of the proposed filters. We also address a framework to implement multiplierless filters and to compensate for the passband droop introduced by this class of filters. For increased flexibility, we generalize the transfer function by allowing different orders between the two stages of decimation.The paper presents many examples to clearly describe the design procedure. Comparisons are also given with the goal of contrasting the magnitude responses of the proposed filters with the ones of three other techniques recently proposed in the literature, as well as with classical comb filters.

Bit-Level Multiplierless FIR Filter Optimization Incorporating Sparse Filter Technique

Multiplierless FIR filter optimization has been extensively studied in the past decades to minimize the number of adders. A more accurate measurement of the implementation complexity is the number of full adders counted at bit-level. However, the high computational complexity of the optimization at bit-level hinders the technique from practical applications. In this paper, the sparse filter technique is exploited and makes the search space at bit-level significantly reduced. Thus, the bit-level optimization of multiplierless FIR filters for the first time becomes possible. When the sparse filter technique is employed for the multiplierless filter design, the sparsity of the filter is properly controlled so that the feasibility of the bit-level optimization in discrete space is maintained. Thereafter, in the reduced search space, a tree search algorithm is formulated at bit-level, and techniques to estimate the bit level hardware cost and to accelerate the search are presented. Design examples show that the proposed bit-level optimization method generates designs with lower hardware cost and power consumption than that of the best word-level optimization methods, while the design time is still at an acceptable level. The average power savings to 3 recent published techniques are 13.6%, 8.0% and 26.1%, respectively.

Multiplierless filter‐bank based multicarrier system by using canonical signed digit representation

ABSTRACTThe filter‐bank based multicarrier (FBMC) system is a candidate for designing the physical layer of a cognitive radio because of its spectral efficiency and the spectral containment. The main drawback of such a system compared with orthogonal frequency division multiplexing systems is its high computation complexity, because each subcarrier is shaped by a non‐rectangular prototype filter. Although poly‐phase decomposition is suggested to decrease the sampling rate of filtering, the number of filtering operations (multiplications) is dramatically increased by the growing number of subcarriers and the amount of the desired spectral containment. Hence, hardware implementation of the FBMC system faces challenges such as high electrical power consumption and large silicon area occupation. In order to reduce computational complexity, a multiplierless filter design based on the canonical signed digit (CSD) representation is proposed. In this technique, at first, a prototype filter is designed. Then a pre‐optimization step is employed to adapt the prototype filter coefficients to system objectives and produce an enriched initial seed for genetic algorithm (GA) optimization. Finally, a customized GA is employed to jointly optimize and synthesize filter coefficients into the finite precision CSD representation so that the system objectives such as intersymbol‐interference, interchannel‐interference, and stop‐band attenuation remain unchanged against the full‐precision representation of coefficients. Copyright © 2014 John Wiley & Sons, Ltd.

FIR Filter Design Based on Successive Approximation of Vectors

We present a novel method for the design of finite im- pulse response (FIR) filters with discrete coefficients that belong in thesumofpowers-of-two(POT)space.Theimportanceofthisclass of filters cannot be overstated, given the ever-increasing number of applications for which a specific hardware implementation is needed. Filters that have coefficients that belong to such a class are also referred to as multiplierless filters, given that the oper- ations performed by the filter can all be implemented by using appropriately designed shifts of the input data, making them a perfect choice whenever implementation simplicity and processing speed are the ultimate goal. To produce suc had esign, we employ a vector successive approximation technique successfully used in data compression that has a very low computational complexity, the Matching Pursuits Generalized BitPlanes algorithm (MPGBP). We derive optimality conditions for the approximation dictionary. We compare filters obtained with the proposed method with those derived in previous works. Based on this comparative analysis, we show that this new and powerful way of producing the filters' co- efficients is also among the simplest available in the literature. IndexTerms—Signalprocessing,filterdesign,successiveapprox- imation methods, VQ.

Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool

Retiming is a transformation which can be applied to digital filter blocks that can increase the clock frequency. This transformation requires computation of critical path and shortest path at various stages. In literature, this problem is addressed at multiple points. However, very little attention is given to path solver blocks in retiming transformation algorithm which takes up most of the computation time. In this paper, we address the problem of optimizing the speed of path solvers in retiming transformation by introducing high level synthesis of path solver algorithm architectures on FPGA and a computer aided design tool. Filters have their combination blocks as adders, multipliers, and delay elements. Avoiding costly multipliers is very much needed for filter hardware implementation. This can be achieved efficiently by using multiplierless MCM technique. In the present work, retiming which is a high level synthesis optimization method is combined with multiplierless filter implementations using MCM algorithm. It is seen that retiming multiplierless designs gives better performance in terms of operating frequency. This paper also compares various retiming techniques for multiplierless digital filter design with respect to VLSI performance metrics such as area, speed, and power.

Design of multiplier-less sharp transition width non-uniform filter banks using gravitational search algorithm

In this paper, multiplier-less near-perfect reconstruction tree-structured filter banks are proposed. Filters with sharp transition width are preferred in filter banks in order to reduce the aliasing between adjacent channels. When sharp transition width filters are designed as conventional finite impulse response filters, the order of the filters will become very high leading to increased complexity. The frequency response masking (FRM) method is known to result in linear-phase sharp transition width filters with low complexity. It is found that the proposed design method, which is based on FRM, gives better results compared to the earlier reported results, in terms of the number of multipliers when sharp transition width filter banks are needed. To further reduce the complexity and power consumption, the tree-structured filter bank is made totally multiplier-less by converting the continuous filter bank coefficients to finite precision coefficients in the signed power of two space. This may lead to performance degradation and calls for the use of a suitable optimisation technique. In this paper, gravitational search algorithm is proposed to be used in the design of the multiplier-less tree-structured uniform as well as non-uniform filter banks. This design method results in uniform and non-uniform filter banks which are simple, alias-free, linear phase and multiplier-less and have sharp transition width.

Trigonometrical approach to design a simple wideband comb compensator

This paper presents a trigonometrical approach to design a simple second order wideband compensator of a comb decimation filter. The method is based on the similarity of the inverse passband comb characteristic and the squared sine function. The design parameter B, which is the amplitude of the squared sine function, depends only on the number K of the cascaded comb filters. Considering that the parameter B can be expressed in terms of only addition and shift operations, we may obtain a multiplierless filter. The proposed filter performs wideband compensation efficiently using a maximum of four additions/subtractions, and for a given K, can be applied to any value of the decimation factor M.