Abstract

In all the DSP(Digital Signal Processing) blocks such as digital filters, the filter coefficients are known before hand. Hence, full flexibility of the multiplier is not necessary. Multiplierless Multiple Constant Multiplication(MCM) technique can be used along with retiming for better digital filter optimization.This method is more efficient when compared to shift and add multiplications as intermediate results in MCM technique can be shared which reduces the area of multiplierless implementation of digital filters. The multiplierless filter circuit is further retimed to reduce the overall clock period which increases the clock frequency. Critical path and shortest path computations consume most of the time in retiming computation. The retiming minimizes the overall clock period by reducing the filter critical path. In the general purpose processor where actual retiming vectors are computed for digital filters, the speed with which the retiming transformation is performed suffers as the entire transformation code will be written in the form of a soft core. Hence, FPGA based path solver architecture are proposed in this paper can reduces the burden on general purpose processors while retiming. This work contributes to reduced processing time for retiming using FPGA based path solvers. Due to complexity and transistor size reduction, designing of VLSI architectures for DSP blocks has become very challenging. Automated Tools are required most often to introduce the products to market in a timely manner and to make the VLSI designs more stable, reliable and tractable. A framework called DiFiDOT(Digital Filter Design Optimization Tool) is developed in this work for synthesizing the optimized filter architectures. Finally, an application for Electrocardiography(ECG) is designed using MCM based retimed digital filters to remove the power supply interference, baseline drift and the broadband noise from the ECG signal.

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