Multiplexer Research Articles

InP DHBT Based IC Technology for over 80 Gbit/s Data Communications

In this paper, we report a manufacturable InP DHBT technology, suitable for medium scale mixed-signal and monolithic microwave integrated circuits. The InGaAs/InP DHBTs were grown by MBE and fabricated using conventional process techniques. Devices with an emitter junction area of 4.8μm 2 exhibited peak cutoff frequency (f T ) and maximum oscillation frequency (f MAX ) values of 265 and 305 GHz, respectively, and a breakdown voltage (BV CEo ) of over 5 V. Using this technology, a set of mixed-signal IC building blocks for > 80Gbit/s fibre optical links, including distributed amplifiers (DA), voltage controlled oscillators (VCO), and multiplexers (MUX), have been successfully fabricated and operated at 80 Gbit/s and beyond.

Design and performance evaluation of a 156‐Mb/s point‐to‐multipoint millimeter‐wave fiber‐radio access link

AbstractA 60‐GHz point‐to‐multipoint (P‐MP) fiber‐radio access link with data rate of 156 Mb/s is presented. For a compact system configuration, a small‐size 60‐GHz transceiver module with planar antennas is developed. A point‐to‐point (P‐P) full‐duplex fiber‐optic configuration is extended to the scheme with multiple access points (APs) by using a tree coupler and a dense wavelength‐division multiplexing (DWDM) multiplexer (MUX). The bit error rate (BER) performances of the 60‐GHz fiber‐radio access link are measured and compared. Furthermore, the effect of the extension to the scheme with multiple APs is evaluated. © 2006 Wiley Periodicals, Inc. Microwave Opt Technol Lett 48: 1219–1222, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21576

Low supply voltage operation of over-40-Gb/s digital ICs based on parallel-current-switching latch circuitry

We implemented a low-voltage latch circuit topology in a full-rate 4:1 multiplexer (MUX) using InP-HBT technology. The proposed latch circuitry incorporates parallel current switching together with inductive peaking a combination that makes it suitable for over-40-Gb/s operation at supply voltages ranging from 1.5 to 1.8 V. The full-rate 4:1 MUX provided 40-Gb/s error-free operation with a power dissipation of only 1 W at a supply voltage of 1.8 V. The D-flip/flop (D-F/F) based on this latch circuitry provided 50-Gb/s D-F/F operation at a supply voltage as low as 1.5 V. Demultiplexing operation was also confirmed for the D-F/F with this circuit technology at a data rate of up to 110Gb/s with a 1.8-V supply voltage. The latch circuitry should help enable development of a low-voltage 40-Gb/s full-rate module which can be seamlessly connected with high-speed CMOS I/O circuits.

RECENT PROGRESS IN 40- TO 100-GBIT/S-CLASS OPTICAL COMMUNICATIONS ICS USING INP-BASED HBT TECHNOLOGIES

This paper describes our InP-based heterojunction bipolar transistor (HBT) technologies and circuit design techniques for small-scale-integration (SSI) and medium-scale-integration (MSI) circuits for 40- to 100-Gbit/s-class optical communications systems. The circuits include a sub-4-ps emitter-coupled logic (ECL) gate, 100-Gbit/s selector circuit, 90-Gbit/s decision circuit, 50-Gbit/s 4:1 multiplexer (MUX) and 1:4 demultiplexer (DEMUX) ICs, aver-40-Gbit/s 16:1 MUX IC, and 40-Gbit/s full-clock-rate DEMUX with a clock and data recovery (CDR) circuit. This paper demonstrates that InP-based HBT technologies and our circuit design techniques are attractive for fabricating ultrahigh-speed SSI circuits with data rates approaching 100 Gbit/s and low-power MSI circuits with data rates of over 40 Gbit/s.

Over 80 Gbit/s 2:1 multiplexer and low power selector ICs using InP/InGaAs DHBTs

A 2:1 multiplexer (MUX) and low power selector ICs have been successfully designed and manufactured using an InP/InGaAs DHBT technology. The 2:1 MUX has been tested at data rates up to 80 Gbit/s with an output swing of 600 mV, while the selector IC has achieved operation speed up to 90 Gbit/s at a power consumption of only 385 mW.

SiGe-HBT-based 54-gb/s 4:1 multiplexer IC with full-rate clock for serial communication systems

A 4:1 multiplexer (MUX) IC for 40 Gb/s and above operations in optical fiber link systems has been developed. The ICs are based on 122-GHz-f/sub T/ 0.2-/spl mu/m self-aligned selective-epitaxial-growth SiGe HBT technology. To reduce output jitter caused by clock duty distortion, a master-slave delayed flip-flop (MS-DFF) with full-rate clock for data retiming is used at the final stage of the MUX IC. In the timing design of the critical circuit for full-rate clocking, robust timing design that has a wide timing margin between data and clock at the MS-DFF was achieved. Measurements using on-wafer probes showed that the MUX attained 54-Gb/s operation with an output voltage-swing of 400 mVpp. The output rms jitter generated by the MUX was 0.91 ps and tr/tf (10%-90%) was 11.4/11.3 ps at a data rate of 50 Gb/s. Power consumption of the IC was 2.95 W at a power supply of -4.8 V. Error-free operation (<10/sup -12/) in back-to-back configuration of the MUX and a 1:4 DEMUX IC module at a data rate of 45 Gb/s was confirmed. We therefore concluded that the MUX IC can be applied for transmitter functions in optical-fiber-link systems at a data rate of 40 Gb/s and higher for forward error correction.

A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os

A 0.622-8-Gb/s clock and data recovery (CDR) circuit using injection locking for jitter suppression and phase interpolation in high-bandwidth system-on-chip solutions is described. A slave injection locked oscillator (SILO) is locked to a tracking aperture-multiplying DLL (TA-MDLL) via a coarse phase selection multiplexer (MUX). For the fine timing vernier, an interpolator DAC controls the injection strength of the MUX output into the SILO. This 1.2-V 0.13-/spl mu/m CMOS CDR consumes 33 mW at 8Gb/s. Die area including voltage regulator is 0.08 mm/sup 2/. Recovered clock jitter is 49 ps pk-pk at a 200-ppm bit-rate offset.

A 30-gb/s 70-mW one-stage 4:1 multiplexer in 0.13-/spl mu/m CMOS

A completely integrated 4:1 multiplexer for high-speed operation and low power consumption is presented. The circuit uses a new architecture where four data streams are multiplexed in one stage. Pulses with a duty cycle of 25% switch the inputs to the multiplexer (MUX) output. The pulses are generated from the clock signal and the divided clock signal. Measurement results show the performance of the IQ divider. Current-mode logic is used because of the higher speed compared to static CMOS and the robustness against common-mode disturbances. The multiplexer uses no output buffer and directly drives the 50-/spl Omega/ environment. The lower number of gates compared to the conventional tree topology enables low-power design. Relaxed timing conditions are additional benefits of the one-stage MUX topology. The IC is fabricated in a 0.13-/spl mu/m standard bulk CMOS technology and uses 1.5-V supply voltage. The MUX works up to 30 Gb/s and consumes 70 mW.

50-Gbit/s InP HEMT 4 : 1 multiplexer/1 : 4 demultiplexer chip set with a multiphase clock architecture

A 50-Gbit/s InP high electron-mobility transistor (HEMT) chip set of 4 : 1 multiplexer (MUX) and 1 : 4 demultiplexer (DMUX) integrated circuits (ICs) with a multiphase clock (MPC) architecture is described. The MPC architecture employs a quarter-rate four-phase clock generated by a toggle flip-flop inside the ICs, which reduces the number of circuit elements and lowers the power consumption. The fabricated 4 : 1 MUX and 1 : 4 DMUX ICs exhibited 50-Gbit/s error-free operations for 2/sup 31/-1 pseudorandom bit sequences with 1.71- and 1.42-W power consumption, respectively. Compared to conventional tree-type 4 : 1 MUX and 1 : 4 DMUX ICs using InP HEMTs, the MPC 4 : 1 MUX and 1 : 4 DMUX ICs operate at the same operating speed with less than one-third power consumption.

40-43-gb/s oc-768 16:1 MUX/CMU chipset with SFI-5 compliance

In this paper, we present two copackaged ICs that provide complete OC-768 16:1 multiplexer (MUX) and clock multiplying unit (CMU) functionality. The 17-input 2.5-2.68-Gb/s parallel interface is Serdes Framer Interface Level 5 (SFI-5) compliant while the 40-43-Gb/s output satisfies OC-768 jitter generation specifications with 7 dB of margin. The system architecture and two-chip partitioning are discussed, followed by descriptions of the design challenges including SFI-5 compliance, 40-Gb/s MUX timing, and 20-GHz clock generation. A novel technique for stabilizing timing margins in the final high-speed multiplexer stage using in-phase and quadrature clocks is also presented. This chipset accommodates 11 bits of static skew and 21 bits of dynamic wander at the SFI-5 interface, while generating 125 fs rms of random jitter and 3.1 ps peak-to-peak of deterministic jitter at its 40-43-Gb/s outputs. The measured bit-error ratio is less than 10/sup -15/ for 2/sup 31/-1 PRBS data and is measurement time limited. The two chips occupy 15.6 mm/sup 2/ and 8.25 mm/sup 2/ of die area. Both are implemented in a 120-GHz f/sub T/ SiGe BiCMOS process.

4-bit multiplexer/demultiplexer chip set for 40-gbit/s optical communication systems

We have designed and fabricated a low-power 4:1 multiplexer (MUX), 1:4 demultiplexer (DEMUX) and full-clock-rate 1:4 DEMUX with a clock and data recovery (CDR) circuit using undoped-emitter InP-InGaAs HBTs. Our HBTs exhibit an f/sub T/ of approximately 150 GHz and an f/sub max/ of approximately 200 GHz at a collector current density of 50 kA/spl mu/m/sup 2/. In the circuit design, we utilize emitter-coupled logic and current-mode logic series gate flip-flops and optimized the collector current density of each transistor to achieve low-power operation at required high bit rates. Error-free operation at bit rates of up to 50 Gbit/s were confirmed for the 4:1 MUX and 1:4 DEMUX, which dissipates 2.3 and 2.5 W, respectively. In addition, the full-clock-rate 1:4 DEMUX with the CDR achieved 40-Gbit/s error-free operation.

50-Gb/s 4-b multiplexer/demultiplexer chip set using InP HEMTs

A 50-Gb/s 4:1 multiplexer (MUX) and 1:4 demultiplexer (DEMUX) chip set using InP high electron mobility transistors (HEMTs) is described. In order to achieve wide-range bit-rate operation from several to 50 Gb/s, timing design inside the ICs was precisely executed. The packaged MUX operated from 4 to 50Gb/s with >1-V/sub pp/ output amplitude, and the DEMUX exhibited >180/spl deg/ phase margin from 4 to 50 Gb/s for 2/sup 31/-1 pseudorandom bit sequence (PRBS). Furthermore, 50-Gb/s back-to-back error-free operation for 2/sup 31/-1 PRBS was confirmed with the packaged MUX and DEMUX.

Over 40 Gbit/s 16:1 multiplexer IC using InP/InGaAs HBT technology

A low-power 16:1 multiplexer (MUX) IC using undoped-emitter InP/InGaAs heterojunction bipolar transistors (HBTs) has been successfully designed and fabricated. To minimise power consumption, the collector current density of each HBT was optimised taking into account the required operating speed and the number of fan-outs. Up to 47 Gbit/s error-free operation was confirmed with low power consumption of about 3.2 W. These results demonstrate that InP/InGaAs HBT technology is attractive for fabricating over 40 Gbit/s, low-power medium-scale-integration (MSI) circuits.

A frequency-domain SQUID multiplexer for arrays of transition-edge superconducting sensors

We describe the development of a frequency-domain multiplexer (MUX) to read out arrays of superconducting transition-edge sensors (TES). Fabrication of large-format arrays of these sensors is becoming practical; however, reading out each sensor in the array is a major instrumental challenge. Frequency-domain multiplexing can greatly simplify the instrumentation of large arrays by reducing the number of SQUID's (superconducting quantum interference devices) and wires to the low temperature stages. Each sensor is AC biased at a different frequency, ranging from 380 kHz to 1 MHz. Each sensor signal amplitude-modulates its respective AC bias frequency. An LC filter associated with each sensor suppresses Johnson noise from the other sensors. The signals are combined at a current summing node and measured by a single SQUID. The individual signals from each sensor are then lock-in detected by room temperature electronics. Test chips with fully lithographed LC filters for up to 32 channels have been designed and fabricated. The capacitance and inductance values have been measured and are close to the design goals. We discuss the basic principles of frequency-domain multiplexing, the design and testing of the test chips, and the implementation of a practical system.

A 43-Gb/s full-rate-clock 4:1 multiplexer in InP-based HEMT technology

This paper describes a full-rate-clock 4:1 multiplexer (MUX) in a 0.13-/spl mu/m InP-based HEMT technology for 40-Gb/s and above optical fiber link systems. To reduce output jitter, the serialized data are retimed at the final stage by a retimer, a D-type flip-flop, which has a symmetric layout with an optimized spacing to the ground that minimizes coupling capacitances. A phase adjuster, composed of an exclusive OR and a delay switch, uses external control signals to change each phase of the serialized data and clock entering the retimer and gives a correct timing for the clock to drive the retimer. A clock distributor with a simple wired splitter divides the clock into two clocks with high gain and low current. The MUX integrates 1355 HEMTs formed using electron beam lithography. A chip mounted in a test module operated at up to 47 Gb/s with a power consumption of 7.9 W for a single supply voltage of -5.2 V.

Design of multiplexer in amorphous silicon technology

The large area capability of amorphous silicon technology finds many active matrix displays and imaging arrays employing the a-Si:H thin film transistors (TFTs) as analog switches. The TFTs are limited to simple switching applications due to the low driving current and metastability issues inherent to a-Si:H technology. The most apparent metastability issue in an a-Si:H TFT is threshold voltage (Vt) shift due to prolonged gate bias. The Vt shift is more pronounced for positive gate biases than for negative gate biases. Moreover, in the presence of a pulse gate bias, the Vt shift depends on the frequency of operation. Considering the large number of gate and data lines in displays and imaging arrays, multiplexer circuits can provide benefits such as reducing the pin count of the array, reducing the number of external chips and hence, overall system cost. In amorphous silicon technology, Pass transistor logic (PTL)-based multiplexers (MUXes) are attractive since they can be designed to have manageable Vt shifts and less transistors than logic gates based MUXes. In this article, we present Vt shift measurements on in-house fabricated a-Si:H TFTs under relevant bias conditions and analyze the performance of a PTL-based MUX circuit in a-Si:H technology.

Bidirectional wavelength add/drop multiplexer using two separate MUX and DEMUX pairs and reflection-type comb filters

A bidirectional wavelength add/drop multiplexer (B-WADM) using two separate multiplexer (MUX), demultiplexer (DEMUX) pairs and reflection-type comb filters (RCFs) is proposed and demonstrated. The proposed B-WADM alleviates the formerly stringent requirement on MUX/DEMUX crosstalk characteristics, while suppressing the power penalty induced by Rayleigh backscattering/optical reflection. Two types of RCFs are proposed based on fiber Bragg gratings and a reciprocal wavelength interleaver, respectively. Experimentally, a combination of an array of fiber Bragg gratings and a light absorber was used as an RCF. The measured crosstalk induced by the Rayleigh backscattering was successfully suppressed to a negligible level (−30 dB) while simultaneously achieving a high B-WADM span gain over 25 dB.

EVALUATION OF A LOW COST, HIGH CAPACITY ELECTRONIC THERMOCOUPLE SELECTION UNIT

Two laboratory experiments and one field experiment were conducted to evaluate a new, portable temperatureacquisition and multiplexing (MUX) system that has the ability to read many thermocouples at very low cost per channel.Although commercial units are available to multiplex thermocouples , switching many channels (on the order of 100 or more)can become costprohibitive. For our studies, an eightchannel system was built and designed to be easily expandable. Thesystem is a modified version of one already documented, which uses CMOS electronic switches instead of electromechanicalrelays to select channels. Laboratory experiments were conducted to evaluate temperature responses of readings from severalchannels, evaluate the influence of channels on readings from other channels by placing the sensors in different thermalenvironments, and to determine the effect of MUX circuitry on readings. Results of analysis indicated no significantinteractions between thermocouples and channels, but channels reading the same ambient environment showed statisticallysignificant differences at the 1% level. Most deviations between channel readings were below 0.4
C with a maximumdeviation of 0.6
C. Crosstalk between channels was not apparent, which is consistent with previous observations. Readingsfrom thermocouples connected to MUX units averaged 0.1
C higher than those connected to manualreading meter. Standarddeviation of reading differences was 0.22
C. In an experiment for ozonebased water purification, thermocouples wereplaced in a thermal environment down to
160
C to verify the systems performance and to examine amplifier characteristicsat very low temperatures. Temperatures tracked a published response curve for the amplifier well down to
160
C and thethermocouple measuring system appeared to be temporally stable from spot checks on system drift. The system describedshould be suitable for measuring relative temperature differences, and will be useful in facilitating research requiringintensive temperature measurement at low cost.

A 50-GHz static frequency divider and 40-Gb/s MUX/DEMUX using self-aligned selective-epitaxial-growth SiGe HBTs with 8-ps ECL

A static frequency divider with a maximum operating frequency of up to 50 GHz and a multiplexer (MUX) and a demultiplexer (DEMUX) that both operate at 40 Gb/s were developed for future optical-fiber-link systems. These digital circuits were fabricated using ultra-high-speed self-aligned selective-epitaxial-growth SiGe-base hetero-junction bipolar transistors (HBTs) with self-aligned stacked metal/in-situ doped poly-Si electrodes. These HBTs provide a 95-GHz cutoff frequency, a 108-GHz maximum oscillation frequency, and a minimum emitter-coupled-logic (ECL) gate delay of 8 ps. The excellent results from this digital chipset show that SiGe HBT technology, with its high reliability and cost-effectiveness, will play an important role in future multi-gigabit per second optical-fiber-link systems.

0.18-μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation

A feedback MOS current mode logic (MCML) is proposed for the high-speed operation of CMOS transistors. This logic is more tolerant to the threshold voltage fluctuation than the conventional MCML and is suitable for gigahertz operation of deep-submicron CMOS transistors. Using this logic, 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) ICs for optical-fiber-link systems have been fabricated with 0.18-/spl mu/m CMOS transistors. The ICs are faster than conventional CMOS MUX and DEMUX ICs and their power consumption is less than 1/4 of that of the conventional 10-Gb/s MUX and DEMUX ICs made using Si bipolar or GaAs transistors.