Multiple-valued Logic Functions Research Articles

An Improved Local Search Learning Method for Multiple-Valued Logic Network Minimization with Bi-objectives

SUMMARY This paper describes an improved local search method for synthesizing arbitrary Multiple-Valued Logic (MVL) function. In our approach, the MVL function is mapped from its algebraic presentation (sumof-products form) on a multiple-layered network based on the functional completeness property. The output of the network is evaluated based on two metrics of correctness and optimality. A local search embedded with chaotic dynamics is utilized to train the network in order to minimize the MVL functions. With the characteristics of pseudo-randomness, ergodicity and irregularity, both the search sequence and solution neighbourhood generated by chaotic variables enables the system to avoid local minimum settling and improves the solution quality. Simulation results based on 2variable 4-valued MVL functions and some other large instances also show that the improved local search learning algorithm outperforms the traditional methods in terms of the correctness and the average number of product terms required to realize a given MVL function.

Protected optical line coding based on multiple-valued logics

Multiple-valued logic functions given by the Allen-Givone algebra are proposed for use in optical nonquantum communication channels as tools for generating a set of secret keys of very high dimension.

Non-binary functional synthesis using ACO-based heuristic

Multiple-valued logic (MVL) synthesis is a problem that has attracted increased interest in recent years. The MVL synthesis problem is more involved compared to its binary counterpart. The search space for finding optimal MVL functional synthesis is enormous. Conventional deterministic methods for MVL functional synthesis are prohibitively expensive, indicating an eminent need for the use of iterative heuristic-based synthesis techniques. In this paper, an ant colony optimization (ACO) based heuristic algorithm for synthesis of MVL functions is proposed. The algorithm mimics the ants' behaviour in the real world. Real ants are found to be able to select the shortest path between their nest and food sources in the existence of alternate paths, or even hurdles between the two. The proposed ACO algorithm uses some of the known real ant techniques in finding the shortest paths to the (near) optimal number of product terms that can cover the minterms of a given MVL function. The proposed algorithm is tested using 50 000 randomly generated 2-variable 4-valued functions. The results obtained using the proposed approach show that the proposed approach outperforms existing direct cover (DC) techniques in terms of the average number of product terms (implicants) required to synthesize a given MVL function.

Circuit testable design and universal test sets for multiple-valued logic functions

The circuit testable realizations of multiple-valued functions are studied in this letter. First of all, it is shown that one vector detects all skew faults in multiplication modulo circuits or in addition modulo circuits, and n+1 vectors detect all skew faults in the circuit realization of multiple-valued functions with n inputs. Secondly, min(max) bridging fault test sets with n+2 vectors are presented for the circuit realizations of multiple-valued logic functions. Finally, a tree structure is used instead of cascade structure to reduce the delay in the circuit realization, it is shown that three vectors are sufficient to detect all single stuck-at faults in the tree structure realization of multiple-valued logic functions.

다치 함수의 차분을 이용한 상황 인식 모델 및 응용

최근 유비쿼터스 컴퓨팅 환경에서 핵심적인 요소 기술인 상황 인식 시스템을 실현하기 위해 필요한 상황 정보를 수집하는데 점차 센서의 활용과 응용분야가 확대되고 있다. 상황 인식 서비스는 센서로부터 수집된 상황 정보를 통합하고 해석 및 추론 과정을 거쳐 사용자에게 상황에 따라 적절한 서비스를 제공하는 것으로 매장, 의료, 교육 등의 응용분야에서 많이 연구되고 있다. 본 논문에서는 다치 함수의 차분 및 구조적 성질을 이용하여 주변 상황 등을 인식하는 방법과 그 인식 결과를 해석하여 주변상황의 변화에 따른 적절한 서비스를 제공할 수 있는 모델을 제안하고 적용 예를 통하여 확인한다. The Context-Aware system is the core technology in the Ubiquitous Computing Environment. Recently, the practical use of a sensor is magnified and the application fields of it are gradually extended in order to collect necessary context information. Context-Aware service integrates the context information which is collected by sensors, and then provides, a suitable service to a user through the process of analysis and reasoning. This service is studied in a variety of fields such as marketing, medical treatment, education and so on. In this paper, we analyze the method of recognizing surrounding context and the result of the awareness by using differential and structural property of multiple valued logic function; propose the model that provides appropriate service depending on the change of surrounding contort; confirm the applicability of the Context-aware system by showing the example of application.

Three-dimensional lattice logic circuits, Part III: Solving 3D volume congestion problem

This part is a continuation of the first and second parts of my paper. In a previous work, symmetry indices have been related to regular logic circuits for the realization of logic functions. In this paper, a more general treatment that produces 3D regular lattice circuits using operations on symmetry indices is presented. A new decomposition called the Iterative Symmetry Indices Decomposition (ISID) is implemented for the 3D design of lattice circuits. The synthesis of regular two-dimensional circuits using ISID has been introduced previously, and the synthesis of area-specific circuits using ISID has been demonstrated. The new multiple-valued ISID algorithm can have several applications such as: (1) multi-stage decompositions of multiple valued logic functions for various lattice circuit layout optimizations, and (2) the new method is useful for the synthesis of ternary functions using three-dimensional regular lattice circuits whenever volume-specific layout constraints have to be satisfied.

Realisation of multiple-valued functions using the capacitive threshold logic gate

The circuit-level hardware realisation of several multiple-valued logic functions using the capacitive threshold logic design style is presented. The generic design approach for multiple-input, multiple-output and multiple-level transfer functions is shown. SPICE simulations of complex operators demonstrate correct operation which qualifies the proposed circuits for integration into larger multiple-valued logic systems. An analysis of noise margin figures and comparisons with previously published circuit examples are provided.

Extended regular ternary logic functions and majority functions capable of synthesizing any ternary logic function

AbstractMultiple‐valued logic functions using only AND, OR, and NOT as operators are called Kleenean functions. They were actively studied in Japan beginning in the early 1990s. Previously, regular ternary logic functions corresponding to the ambiguous state in which the truth value 1/2 is neither 0 nor 1 were defined in ternary logic; but regular ternary logic functions are equivalent to ternary Kleenean functions. Regular ternary logic functions represent only a small fraction of all ternary logic functions, and only a part of the ternary logic functions can be synthesized. In this paper we define regular ternary logic functions of the zeroth to third kinds by introducing the cyclical operation. We then define majority functions of the zeroth to third kinds, which are a subset of the extended regular ternary logic functions, and show that any ternary logic function can be synthesized by means of these three majority functions. Finally, using a genetic algorithm as the base algorithm, we present a technique for synthesizing any ternary logic function by means of extended ternary majority elements, and give illustrative examples. © 2003 Wiley Periodicals, Inc. Syst Comp Jpn, 35(1): 79–90, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/scj.10226

Knowledge Discovery from Decision Tables by the Use of Multiple-Valued Logic

This paper describes how succinct rules, which reduce the size of decision tables, can be found by employing multiple-valued logic (MVL). Two multiple-valued algebras are described, one based on level detection, and the other on literal functions. Then a decision table which had also been reduced in size using rough set theory, is now reduced using both algebras and it is seen that all three approaches lead to reductions of comparable simplicity. The new methods require coding the values of each attribute as integers. Then an MVL function that maps the coding of the condition attributes to the coding of the decision attribute is found. As the coded table is sparse only some of the basis functions for each algebra are required. Then a simple approach requiring the reduction of a matrix to row echelon form is used to finding all suitable MVL functions. By decomposing a function in terms of its variables a complete set of rules can be found. The MVL function encodes the data in a very compact form and its decomposition into subfunctions reveals a good way to slice up the table into subtables. The structure of the subfunctions can then be used to simplify each subtable until compact sets of rules emerge. Alternatively, rules can be found by substitution into the MVL function. Encoding a decision table using MVL makes the data easy to manipulate and can uncover relationships that may not become apparent when using other methods.

On complexity of representation of multiple-valued logic functions as polarised polynomials

AbstractThe notion of a polarised polynomial form is extended to the case of multiple-valued logic functions. We introduce the Shannon functions of weight and length of polarised polynomial forms of multiple-valued logic functions and give some bounds for them.

STRIP - a strip-based neural-network growth algorithm for learning multiple-valued functions

We consider the problem of synthesizing multiple-valued logic functions by neural networks. A genetic algorithm (GA) which finds the longest strip in V is a subset of K(n) is described. A strip contains points located between two parallel hyperplanes. Repeated application of GA partitions the space V into certain number of strips, each of them corresponding to a hidden unit. We construct two neural networks based on these hidden units and show that they correctly compute the given but arbitrary multiple-valued function. Preliminary experimental results are presented and discussed.

Chrestenson spectral characterization of correlation-immunity of multiple-valued logic functions over Z/(m)

Chrestenson spectral characterization of correlation-immunity of multiple-valued logic functions over Z/(m)

Synthesis of MVL functions using input and output assignments

A number of decomposition based mapping techniques are proposed. In these techniques, the synthesis problem is formulated as a mapping from an input matrix to an output matrix. The minimisation is obtained by constructing a 'matching-count matrix'. The entries of the matching-count matrix MC ij represent the number of entry matches between the input variable number i in the input matrix (X) and the output function number j in the output matrix (Y). It then selects those input-output pairings that give the maximum matching count, thus maximising the number of switching operations which can be eliminated in the realisation of multiple-valued logic (MVL) functions. The proposed techniques are classified as: output-phase with complement, input-phase with and without complement. Numerical results are presented to show that the proposed techniques result in significant reduction in the number of switching operators required for the implementation of 5000 randomly generated r-valued functions (for r = 3, 4 and 5). It is also shown that the input-phase assignment techniques do not require any additional hardware circuitry at the output to restore the original function. This may give this technique an edge over other techniques.

A novel multiple-valued logic gate using resonant tunneling devices

We demonstrate a novel multiple-valued logic (MVL) gate using series-connected resonant tunneling devices. Logic operation is based on the control of the switching sequence of these devices through the modulation of their peak currents by the input signal. We obtain the literal function, one of fundamental MVL functions, by integrating three InGaAs-based resonant-tunneling diodes with two HEMT's on an InP substrate. The gate configuration is greatly simplified compared with a conventional literal gate employing CMOS circuits.

Spectral characterization of the correlation-immunity of multiple-valued logic functions

Correlation-immunity is an important concept in cryptology. In ref. [1] Siegenthaler introduced the mathematical definition of correlation-immunity and used the correlation-immunity order of logic functions as a measure for cipher systems to defend against correlation attacks. In terms of Walsh transform, the correlation immunity of binary-valued logic functions, i.e. Boolean functions, was studied in ref. [2], and a necessary

A multiple-valued Reed-Muller transform for incompletely specified functions

This paper considers the Reed-Muller transform for incompletely specified multiple-valued logic functions, which is obtained as the finite field polynomial representation. A new algorithm for dealing with single-variable functions is presented. It is applicable to finite fields of small sizes (two to four), which is of interest because only these fields are readily implementable with today's MVL technology. It is shown how such or any similar single-variable algorithm can be used to obtain a fast n-variable Reed-Muller transform based on this transform, a heuristic scheme is derived for dealing with incompletely specified functions. It has better computational properties than other methods and achieves the best results when applied to functions with a large number of unspecified points.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Spectral analysis of some independences on multiple-valued logical functions on their variables

There are many kinds of special relationships between multiple-valued logical functions and their variables, and they are difficult to be judged from their expressions. In this paper, some sufficient and necessary conditions of the independence and statistical independence of multiple-valued logical functions on their variables are given. Some conditions of algebraic independence of multiple-valued logical functions on some of their variables and the way to degenerate a function to the greatest extent are proposed, and some applications of these results are indicated. All the results are studied by using Chrestenson spectral techniques.

A new structure for CMOS realization of MVL functions

A new structure is proposed for the realization of multiple-valued logic (MVL) functions. Multiple-valued logic levels are represented in terms of current values, which represent the inputs and the outputs of the MVL circuits. Binary voltage signals are generated inside the structure by using a circuit element called threshold. Using these voltage signals and binary operators, such as AND, OR, XOR and inverter, binary voltage signals are obtained and used as control signals for generating the output current levels for the desired MVL function. The realizations of some example MVL circuits using the proposed structure are included along with HSPICE transient analysis simulation results to verify the functionality of the designed circuits.

CMOS multiple-valued logic design. II. Function realization

For pt. I see ibid vol. 40, no. 8 p 503-14 (1993). The performance of the set of operators proposed in pt. I is compared with existing sets of operators for the realization of multiple-valued logic (MVL) functions. In pt. I, a set of operators was proposed consisting of literal, cycle, complement of literal, complement of cycle, min, and tsum operators (Set 1). This set of operators is compared to two existing sets of operators consisting of literal, complement of literal, min, and tsum operators (Set 2) and literal, min, and tsum operators (Set 3). For 3-valued 2-variable MVL functions, it is shown that the maximum number of product terms (PTs) required to realize all functions can be reduced to three PTs (using the Set 1 operators) from five PTs (using the Set 2 operators) and six PTs (using the Set 3 operators). In addition, it is shown that the average number of PTs required to realize all the functions reduces to 2.61 (using the Set 1 operators) from 3.19 (using the Set 2 operators) and 3.61 (using the Set 3 operators). It is anticipated that similar improvements are possible for higher valued logic. Realizations of a 4-valued 2-variable function based on different sets of operators are included to support such a claim. >

SC and pass transistor combined circuits

The pass-transistor structure provides a powerful tool for the implementation of binary and multiple-valued logic (MVL). Circuit realisation of any general MVL function using literals, MAX and MIN is easy. However, the resulting circuits have certain limitations. A combination of pass transistors (PT) with switched-capacitor (SC) circuits is shown to provide useful improvements.