Three-dimensional lattice logic circuits, Part III: Solving 3D volume congestion problem

Abstract

This part is a continuation of the first and second parts of my paper. In a previous work, symmetry indices have been related to regular logic circuits for the realization of logic functions. In this paper, a more general treatment that produces 3D regular lattice circuits using operations on symmetry indices is presented. A new decomposition called the Iterative Symmetry Indices Decomposition (ISID) is implemented for the 3D design of lattice circuits. The synthesis of regular two-dimensional circuits using ISID has been introduced previously, and the synthesis of area-specific circuits using ISID has been demonstrated. The new multiple-valued ISID algorithm can have several applications such as: (1) multi-stage decompositions of multiple valued logic functions for various lattice circuit layout optimizations, and (2) the new method is useful for the synthesis of ternary functions using three-dimensional regular lattice circuits whenever volume-specific layout constraints have to be satisfied.