Multiple Tunnel Junctions Research Articles

Wavelength‐stabilized ns‐pulsed 2.2 kW diode laser bar with multiple active regions and tunnel junctions

The improvement of the performance of a distributed Bragg reflector laser bar emitting near 905 nm through the use of multiple epitaxially stacked active regions and tunnel junctions is reported. The bar consisting of 48 emitters (each having an aperture of 50 µm) emits an optical power of 2.2 kW in 8 ns long pulses at an injection current of 1.1 kA. This corresponds to an almost threefold increase of the pulse power compared to a bar with lasers having only a single active region. Due to the integrated surface Bragg grating, the bar exhibits a narrow spectral bandwidth of about 0.3 nm and a thermal tuning of only 68 pm/K.

High-Density Spin–Orbit Torque Magnetic Random Access Memory With Voltage-Controlled Magnetic Anisotropy/Spin-Transfer Torque Assist

This article explores an area saving scheme for spin–orbit torque (SOT) magnetic random access memory (MRAM) by sharing the SOT channel and write transistor among multiple magnetic tunnel junctions (MTJs). We use two write mechanisms to selectively write the MTJs, i.e., voltage-controlled magnetic anisotropy (VCMA)-assisted write in the presence of an external magnetic field and field-free spin-transfer torque (STT)-assisted write. Using micromagnetic simulations that are augmented by the rare-event enhancement, we study various trade-offs among write current, time, and energy, write error rate (WER), and the number of MTJs on an SOT channel. We quantify the issue of IR drop on the SOT channel as a function of the SOT layer thickness and number of MTJs. Our results show having more than four MTJs on an SOT channel poses major challenges in terms of IR drop and WER. In addition, we evaluate the impact of the proposed scheme on read performance.

Non-Volatile Latch Compatible With Static and Dynamic CMOS for Logic in Memory Applications

To overcome the performance bottleneck of the CMOS-only logic circuits, logic-in-memory (LiM)-based circuits can be used. Herein, the memory and logic are combined to reduce the power requirements and the data access delay. The LiM architecture is proposed to be better in terms of efficiency when compared to the Von-Neumann architecture which is currently being used. In this article, a novel non-volatile (NV) latch is proposed to realize the LiM-based computation. It is compared with previous circuit architectures of the NV latch. The proposed latch consists of multiple magnetic tunnel junctions (MTJs) connected in series which are accessed through an NMOS transistor for reading the data. A cross-coupled inverter (CCI) is used to regenerate the output to the appropriate logic levels using its inherent regenerative action. The proposed latch has a simple design, higher stability, and lower tunnel magnetoresistance (TMR) degradation, and compatibility with static and dynamic CMOS logic styles. Furthermore, the proposed latch is having fewer transistor count in logic implementation which result in minimized area overhead and lower power consumption. The existing write circuit is also modified for writing the MTJs in the proposed NV latch which results in a 29.57% reduction in power consumption for a write margin of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$20 ~\mu \text{A}$ </tex-math></inline-formula> and 34.92% for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$40 ~\mu \text{A}$ </tex-math></inline-formula> write margin. Furthermore, the area requirement of the modified write circuit is found to be significantly lower than that of the existing write circuit.

Reduced Electron Temperature in Silicon Multi-Quantum-Dot Single-Electron Tunneling Devices.

The high-performance room-temperature-operating Si single-electron transistors (SETs) were devised in the form of the multiple quantum-dot (MQD) multiple tunnel junction (MTJ) system. The key device architecture of the Si MQD MTJ system was self-formed along the volumetrically undulated [110] Si nanowire that was fabricated by isotropic wet etching and subsequent oxidation of the e-beam-lithographically patterned [110] Si nanowire. The strong subband modulation in the volumetrically undulated [110] Si nanowire could create both the large quantum level spacings and the high tunnel barriers in the Si MQD MTJ system. Such a device scheme can not only decrease the cotunneling effect, but also reduce the effective electron temperature. These eventually led to the energetic stability for both the Coulomb blockade and the negative differential conductance characteristics at room temperature. The results suggest that the present device scheme (i.e., [110] Si MQD MTJ) holds great promise for the room-temperature demonstration of the high-performance Si SETs.

Internally wavelength stabilized 910 nm diode lasers with epitaxially stacked multiple active regions and tunnel junctions

We present a multi-active-region bipolar-cascade distributed-Bragg reflector (DBR) laser emitting around 910 nm. The three active regions and two tunnel junctions are located in a single waveguide core sharing the same third-order vertical mode. A slope efficiency of 2.25 W/A was measured with a threshold current density of 400 A/cm2. Due to the implemented 7th Bragg order surface grating, the laser exhibits a narrow optical spectrum with a width of 0.3 nm and a thermal detuning of 60 pm/K.

Spintronic Computing-in-Memory Architecture Based on Voltage-Controlled Spin–Orbit Torque Devices for Binary Neural Networks

Binary neural networks (BNNs) are promising for resource-constrained Internet of Things (IoT) devices owing to the lightweight memory and computation requirements. Moreover, BNNs based on computing-in-memory (CIM) architectures have attracted much attention in both algorithm and hardware designs. Recently, a variety of CIM-based BNN hardware designs has been proposed, particularly based on emerging nonvolatile memories (NVMs), which have merits in terms of nonvolatility and intrinsic resistance-based computing capabilities. However, mainstream NVMs utilize the one transistor plus one memory device (1T1M) cell structure, limiting the computing efficiency and throughput. In this article, we propose a high-throughput CIM architecture for BNN hardware based on a voltage-controlled spin–orbit torque (VC-SOT) memory device, which enables parallel programming and computing operations thanks to its specific cell structure. In VC-SOT devices, multiple magnetic tunnel junctions (MTJs) are stacked on a heavy metal and share the same SOT write current. Furthermore, computing can be achieved based on the normal memory-like write and read operations. Based on a physics-based VC-SOT MTJ model, we designed and evaluated the proposed CIM-based key BNN hardware in the 40-nm technology node. Our simulation results validated the parallel programming/computing functionality and illustrated the performance in terms of power consumption (~4 fJ/bit) and speed (~2 ns/write, 0.36–1.5 ns/read).

Novel 900 nm diode lasers with epitaxially stacked multiple active regions and tunnel junctions

A multi-active-region bipolar-cascade edge-emitting laser emitting at nearly 900 nm is presented. The three active regions and two tunnel junctions located in a single waveguide core share the same third-order vertical mode. A slope efficiency of 3.6 W/A was measured with a threshold current density of 230 A/cm2. The epitaxial layer stack developed features with very low internal optical losses of 0.7 cm−1. The voltage extrapolated to vanishing current is only 0.3 V larger than 3 times the voltage of 1.4 V originating from the photon energy.

All-Electrical Control of Scaled Spin Logic Devices Based on Domain Wall Motion

Spin logic devices based on domain wall (DW) motion offer flexible architectures to store and carry logic information in a circuit. In this device concept, information is encoded in the magnetic state of a magnetic track shared by multiple magnetic tunnel junctions (MTJs) and is processed by DW motion. Here, we demonstrate that all-electrical control of such nanoscale DW-based logic devices can be realized using a novel MTJ stack. In addition to field-driven motion, which is isotropic, we show the directional motion of DWs driven by current, a key requirement for logic operation. Full electrical control of an AND logic gate using DW motion is demonstrated. Our devices are fabricated in imec's 300-mm CMOS fab on full wafers, which clears the path for large-scale integration. This proof of concept, thus, offers potential solutions for high-performance and low-power DW-based devices for logic and neuromorphic applications.

Room-temperature high sensitivity of multiple tunnel junctions based on single-charge photodetection

We successfully demonstrate the high stability at room temperature of a new design of single-photon detector based on multiple tunnel junctions with superior responsivity and high quantum efficiency. The single-photon detector uses one-dimensional (1D) multiple tunnel junctions (MTJs) with 12 islands and 13 tunnel junctions coupled with a silicon single-electron box. A single-electron transistor (SET) is used to read the charge state of a silicon quantum dot (Si-QD). The response of the single-photon detector (Si-QD and SET) is directly related to the photoconductivity gain in the MTJs with associated conductance steps produced by individual photocarriers. Numerical simulations confirm the high stability at room temperature of the single-photon detection. Moreover, an analytical model developed in MATLAB that takes account of the thermionic emission of charge carriers confirms the high stability of the single-photon detection at room temperature.

Spin-torque-driven MTJs with extended free layer for logic applications

The development of low-power spintronic computation would open new paths for advanced logic nodes. It could utilize a ferromagnetic free layer shared by multiple magnetic tunnel junctions to cascade spin-coherent information. The basic component of this device would be a magnetic tunnel junction with an extended free layer. Here, we study the magnetization dynamics of such a system. One or multiple intermediate resistance levels are observed during spin-torque-induced magnetization reversal. Micromagnetic modeling suggests that non-uniform magnetic anisotropy introduced by careful pillar-pattering is a plausible cause of this multi-step reversal.

Controlled synthesis and enhanced tunnelling magnetoresistance in oriented Fe3O4 nanorod assemblies

This paper focuses on the effect of shape anisotropy on the magnetic and tunnelling magnetoresistance (TMR) properties of oleylamine-coated magnetite (Fe3O4) nanorod assemblies. Fe3O4 nanorods with a wide variation in length (35–180 nm) and diameter (5.5–24 nm) are obtained by a facile two-step process where β-FeOOH nanorods are first prepared hydrothermally, followed by a transformation to the Fe3O4 phase in an oleylamine medium via a solvo-thermal reaction. An observation of the Verwey transition at 120 K and analyses of Mössbauer spectra indicate that the as-synthesized Fe3O4 nanorods are highly stoichiometric. In an assembly of nanorods, a surface-functionalizing oleylamine layer acts as the insulating dielectric layer to form multiple tunnel junctions between the semi-metallic nanorods, and intergrain tunnelling takes place. A 14% TMR is recorded in the nanorod assemblies at room temperature, which interestingly increases by a factor of 1.4 when the nanorods are pre-aligned under an external magnetic field. For aligned nanorods, the magnetic moments stay in parallel to each other and result in higher spin-polarized current. The observed TMR value increases with a decrease in temperature, and attains a maximum value of 31% at the Verwey transition temperature. Spin polarization of the nanorod assemblies is estimated to be 46% at room temperature.

Engineering Magnetic and Tunneling Magnetoresistance Properties of CoxFe3−xO4 Nanorods

A simple cation exchange reaction has been adapted to produce the CoxFe3−xO4 nanorods with different concentration of Co. The substitution of Fe2+ with Co2+ ions increase the magnetocrystalline anisotropy and coercivity of pristine superparamagnetic Fe3O4 nanorods. Atomic concentration of 5–11% of Co2+ in Fe3O4 nanorods renders coercivity of 300–460 Oe at room temperature and 2200–4050 Oe at 10 K. Hydrocarbon long‐chain amine (oleylamine) functionalized nanorod assemblies form a multiple tunnel junction, where organic amine monolayers act as insulating tunnel barriers. CoxFe3−xO4 nanorods show a magnetoresistance switching behavior at room temperature and the switching field is consistent with the magnetic coercivity. A 14–15% TMR is recorded at room temperature in CoxFe3−xO4 nanorod assemblies, which increases to 23–26% at 150 K at a magnetic field of ±2 T. The calculated spin polarization for Co0.33Fe2.67O4 nanorods at room temperature is 52%. A similar spin polarization and TMR as Fe3O4 in Co‐doped Fe3O4 nanorod assemblies is obtained. Thus, controlled doping of Co ions engineers the coercivity and remanence of the “super‐paramagnetic” Fe3O4 without hindering their TMR performances, which could be very useful for memory devices.

Large tunneling magnetoresistance in octahedral Fe3O4 nanoparticles

We have observed large tunneling Magnetoresistance (TMR) in amine functionalized octahedral nanoparticle assemblies. Amine monolayer on the surface of nanoparticles acts as an insulating barrier between the semimetal Fe3O4 nanoparticles and provides multiple tunnel junctions where inter-granular tunneling is plausible. The tunneling magnetoresistance recorded at room temperature is 38% which increases to 69% at 180 K. When the temperature drops below 150 K, coulomb staircase is observed in the current versus voltage characteristics as the charging energy exceeds the thermal energy. A similar study is also carried out with spherical nanoparticles. A 24% TMR is recorded at room temperature which increases to 41% at 180 K for spherical particles. Mössbauer spectra reveal better stoichiometry for octahedral particles which is attainable due to lesser surface disorder and strong amine coupling at the &amp;lt;111&amp;gt; facets of octahedral Fe3O4 nanoparticles. Less stoichiometric defect in octahedral nanoparticles leads to a higher value of spin polarization and therefore larger TMR in octahedral nanoparticles.

Pushing the limits of concentrated photovoltaic solar cell tunnel junctions in novel high‐efficiency GaAs phototransducers based on a vertical epitaxial heterostructure architecture

AbstractA monolithic compound semiconductor phototransducer optimized for narrow‐band light sources was designed for achieving conversion efficiencies exceeding 50%. The III‐V heterostructure was grown by metal‐organic chemical vapor deposition, based on the vertical stacking of 5 partially absorbing GaAs n/p junctions connected in series with tunnel junctions. The thicknesses of the p‐type base layers of the diodes were engineered for optimal absorption and current matching for an optical input with wavelengths centered near 830 nm. Devices with active areas of ~3.4 mm2 were fabricated and tested with different emitter gridline spacings. The open circuit voltage (Voc) of the electrical output is five times or more than that of a single GaAs n/p junction under similar illumination. The device architecture allows for improved Voc generation in the individual base segments because of efficient carrier extraction while simultaneously maintaining a complete absorption of the input photons with no needs for complicated fabrication processes or reflecting layers. With illumination powers in the range of a few 100 mW, the measured fill factor (FF) varied between 88 and 89%, and the Voc reached over 5.75 V. The data also demonstrated that a proper combination of highly doped emitter and window layers without gridlines is adequate for sustaining such FF values for optical input powers of several hundred milliwatts. As the optical input power is further increased and approaches 2 W (intensities ~58 W/cm2), the multiple tunnel junctions sequentially exceed their peak current densities in the case for which typical (n++)GaInP/ (p++)AlGaAs concentrated photovoltaic tunnel junctions are used. Lower bandgap tunnel junctions designed with improved peak current densities result in phototransducer devices having high FF and conversion efficiencies for up to 5 W optical input powers (intensities ~144 W/cm2). Measurements at different temperatures revealed a Voc reduction of −6 mV/°C at ~59 W/cm2. Copyright © 2015 John Wiley &amp; Sons, Ltd.

DFSTT-MRAM: Dual Functional STT-MRAM Cell Structure for Reliability Enhancement and 3-D MLC Functionality

Spin transfer torque-based magnetic random access memory (STT-MRAM) is considered as one of the most promising candidates for the next generation of nonvolatile memories; however, its storage density and reliability are currently uncompetitive compared with other nonvolatile memories (e.g., NAND flash). In this paper, a dual-functional memory cell structure, named DFSTT-MRAM, is proposed by stacking multiple magnetic tunnel junctions (MTJs) on top of the CMOS access transistor. In such a structure, the cell can be dynamically configured between two possible functional modes, i.e., high-reliability mode (HR-mode) and multilevel cell mode (MLC-mode), based on the data requirements of the addressed applications. The DFSTT-MRAM cell was electrically modeled based on the perpendicular magnetic anisotropy CoFeB/MgO/CoFeB MTJ integrating the STT stochastic switching behaviors. Transient and Monte Carlo simulations were then performed to evaluate its MLC functionality and reliability performance. Our evaluation results show that the DFSTT-MRAM cell can indeed realize MLC capability providing proper write/read control at the MLC-mode and enhance the intrinsic cell reliability by several orders of magnitude when operating at the HR-mode. This cell structure provides a flexible memory cell design for future advanced applications, such as high-density nonvolatile memory and neuromorphic circuits.

Fabrication of room-temperature operational single-electron devices using Au nanoparticles.

Au nanoparticles (5-10 nm in diameter) single electron devices (SEDs) were fabricated utilizing both electron beam lithography and granular film deposition. Both multiple-tunnel junction (MTJ) and double-tunnel junction (DTJ) were fabricated by adjusting the number of Au nanoparticles between the electrodes. Coulomb blockade effects were clearly observed at room temperature from the MTJs. The threshold voltage of the MTJ-SED with a large gap was about 1.5 V, whereas that with a small gap was about 0.8 V, respectively. When the gap was below 20 nm, a periodic Coulomb staircase was observed from the DTJ-SED at room temperature, where the charging energy was about 0.114 eV.

Blue light emitting diode exceeding 100% quantum efficiency

AbstractInGaN/GaN light‐emitting diodes (LEDs) are known to exhibit a strongly non‐uniform vertical carrier distribution within the multi‐quantum well (MQW) active region. We propose to eliminate “dark” quantum wells by insertion of multiple tunnel junctions into the MQW which allow for the repeated use of electrons and holes for photon generation. In good agreement with available measurements, we demonstrate by self‐consistent numerical simulation that such tunnel junction LED design promises quantum efficiencies as high as 250% as well as a strongly enhanced output power at high input power, compared to conventional LED concepts.magnified imageEnergy band diagram and photon emission rate for the proposed LED with four sets of two quantum wells separated by three tunnel junctions.(© 2014 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Theoretical Analysis and Characterization of Multi-Islands Single-Electron Devices with Applications

A two- (2D) and three-dimensional (3D) multiple-tunnel junctions array is investigated. Device structure and electrical characteristics are described. We present a comparison of carriers transport through devices based on polymetallic grains based on master equation and the orthodox theory. The Coulomb blockade effect of 2D and 3D arrays is observed at low and high temperatures. The conduction mechanism is handled by the tunnel effect, and we adopt in addition the thermionic and Fowler-Nordheim emissions. Numerical simulation results focused on flash-memory and photodetector applications. Memory characteristics such as program/erase select gate operation are demonstrated in 2D devices. Also 3D array scheme is discussed for the high-density NCs scalable for photodetector application.

DC and AC Characterization of MgO Magnetic Tunnel Junction Sensors

We have fabricated multiple MgO magnetic tunnel junctions (MTJ) with 1.7 nm oxide, which are connected in series, and layed out in a serpentine geometry. We performed DC tunnel magnetoresistance measurements and AC impedance spectroscopy with crossed DC magnetic fields in the easy and hard axis directions. A simple <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$RLC$</tex></formula> circuit model is used to fit our data and characterize the dependence on capacitance <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(C)$</tex></formula> and inductance <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(L)$</tex></formula> of magnetization orientation of the MTJ sensors. We have found in our samples that <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$C$</tex></formula> and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$L$</tex></formula> are higher in antiparallel than in parallel configuration. We discuss possible reasons for the existence of this field dependence and show the evolution of magnetic field vs. capacitance curve from memory mode into sensing mode at high frequencies.

Design of a Single-Electron Memory Operating at Room Temperature

Single-electronic transistors (SETs) are considered as the attractive component for the next generation of transistors due to their ultrasmall size and low power consumption. Because SETs with single island cannot work at high temperature normally, more researchers begin to carry out research on the SETs with N-dimension multi-islands. In this paper, we introduce a new architecture of single-electron memory; ideally the memory should operate in combination of SETs with a nanowire of two-dimensional regular array of multiple tunnel junctions (MTJs). This structure is analyzed and studied with Monte Carlo simulator, SIMON. The Coulomb blockade effect and thermionic effect play an important role in carrier conduction in the system at room temperature. Nanowire MTJs are used as an electrometer to sense the memory-node charge. The well-defined parameter in tunnel junction circuits helps to obtain the charging of single electrons in these circuits at room temperature.