Multiple Through Silicon Vias Research Articles

A New Data Transmission Method with Low System Overhead Based on Multiple TSV Sub-Arrays

<p indent=0mm>Lots of crosstalk avoidance codes have the forbidden pattern free (FPF) feature. The FPF code suppresses the worst crosstalk with the reasonable codec area, if it is applied to the small-scale through silicon via (TSV) array. The multi-sub-array joint data transmission method is proposed, in order to transmit the data with low system overhead in the large-scale TSV array. Aiming at optimal number of TSV sub-arrays participating in joint data transmission, an optimal design method is proposed based on the analysis of the relationship between the number of TSV sub-arrays and the corresponding system overhead of the joint data transimission scheme. The optimal solution is obtained by theoretical proof. And the codec algorithm of the FPF code in the multi-sub-array joint transmission is further proposed, utilizing the transformation of numeral system. The simulations on the effect of the crosstalk suppression techniques are conducted with multiple sets of electrical TSV parameters. The experimental results show that, the proposed method has not only the lower system overhead, but also advantages on the transmission delay, transmission power and codec area, compared with those of the crosstalk avoidance codes based on Fibonacci numeral system.

Optical Beam-Based Defect Localization Methodologies for Open and Short Failures in Micrometer-Scale 3-D TSV Interconnects

We report laser-based fault isolation methodologies for the localization of open and short failures in $1 \times 5\,\,\mu \text{m}$ via-last through-silicon via (TSV) structures for 3-D system-on-chip (SoC) integration. Due to the photosensitive TSV interconnect capacitance, observation of the photocapacitance response enables nondestructive localization of metallization ruptures. A light-induced capacitance alteration (LICA) measurement is demonstrated on an open failed $1 \times 5\,\,\mu \text{m}$ TSV chain structure with a manufacturing defect. We validate our measurements with active voltage contrast imaging in the scanning electron microscope (SEM) and focused-ion beam (FIB) cross sectioning. Second, TSV dielectric defects generating leakage current between TSV and substrate (i.e., short defects) are detected and localized by sensing the laser-induced TSV photocurrent. An optical beam-induced current (OBIC) measurement is demonstrated on electrically overstressed TSV array structures whereby multiple TSVs are configured in a parallel arrangement. By applying a selective substrate removal process, we can expose the full TSV array and perform optical and tilted SEM inspection and reveal pinhole defects in the TSV liner. We further investigate the effect of breakdown energy on the pinhole formation, relate electrical measurements to SEM inspection, and confirm our results by FIB cross sectioning.

An algorithm for obstacle‐avoiding clock routing tree construction with multiple TSVs on a 3D IC

Effective clock tree design is an important factor for determining chip performance. In this study, the authors present a 3D clock tree design algorithm to enhance the speed and performance of a VLSI chip. The authors propose an algorithm to determine the performance of the clock network by optimising both the clock skew and the dynamic power consumption of the 3D IC clock tree. The authors propose an algorithm for clock tree design based on the Elmore Delay method and routes all the sinks efficiently considering the obstacles with the use of an optimum number of through-silicon-vias (TSVs). The proposed method starts with a segregation technique to divide the sinks into smaller zones. Subsequently, an obstacle avoiding abstract clock tree is constructed with a minimum number of TSVs and buffers. The skew and dynamic power of the tree is calculated. Consequently, the proposed method is compared with recent existing works. The experimental results so obtained are quite encouraging.

Multi-TSV and E-Field Sharing Aware Full-chip Extraction and Mitigation of TSV-to-Wire Coupling

The through-silicon-via (TSV) introduces new parasitic components into 3-D ICs. This paper presents a novel method of extracting the parasitic capacitance between TSVs and their surrounding wires. For the first time, we examine electrical field (E-field) sharing effects from multiple TSVs and neighboring wires and their impact on timing, power, and noise with full-chip sign-off analyses. For fast and accurate full-chip extraction, we propose a pattern-matching algorithm that accounts for the physical dimensions of multiple TSVs and neighboring wires and captures all E-field interactions. Compared with the average error of a field solver, that of our extraction method, which requires only 2.4 s runtime and negligible memory for a full-chip 64-point fast Fourier transform (FFT64) design with 330 TSVs, is 0.063fF. Upon extraction of TSV-related parasitics, we observe that TSV-to-wire capacitance significantly increase average TSV net noise and the longest path delay. To reduce TSV-to-wire coupling, we implement two full-chip optimization methods and show that increasing the minimum distance between TSVs and neighboring wires reduces both coupling noise and the aggressor count. Thanks to E-field sharing from grounded wire guard rings, victim TSVs are more effectively shielded from aggressor noise. A full-chip analysis shows that these methods are highly effective in reducing noise with only slight impact on timing and area.

Tier Adaptive Body Biasing: A Post-Silicon Tuning Method to Minimize Clock Skew Variations in 3-D ICs

In this paper, we analyze the variability in a 3-D clock network designed with single and multiple through-silicon vias and present a post-silicon tuning methodology, called tier adaptive body biasing (TABB), to reduce skew and data path variability in 3-D clock trees. TABB uses specialized on-die sensors to independently detect the process corners of n-channel metal–oxide–semiconductor (nMOS) and p-channel metal–oxide–semiconductor (pMOS) devices and accordingly tune the body biases of nMOS/pMOS devices to reduce the clock skew variability. We also present the system architecture of TABB and circuit techniques for the on-die sensors. Circuit-level simulation and statistical analysis of the TABB architecture in a predictive 45-nm technology demonstrate the effectiveness of TABB in reducing the clock skew variability considering the data path variability in 3-D ICs.

Pre-Bond Probing of Through-Silicon Vias in 3-D Stacked ICs

Through-silicon via (TSV)-based 3-D stacked ICs are becoming increasingly important in the semiconductor industry, yet pre-bond testing of TSVs continues to be difficult with current technologies. In this paper, we present a test and discrete Fourier transform method for pre-bond testing of TSVs using probe technology. We describe the on-die test architecture and probe technique needed for TSV testing, in which individual probe needles make contact with multiple TSVs at a time. We also describe methods for capacitance and resistance measurements, as well as stuck-at and leakage tests. Simulation results using HSPICE are presented for a TSV network. We demonstrate that we can achieve high resolution in these measurements, and therefore high accuracy in defect detection when we target one or multiple TSVs at a time. We also show that the test outcome is reliable even in the presence of process variations or multiple defective TSVs.

Underfill Dispensing for 3D Die Stacking with Through Silicon Vias

In this paper, a 3D stacked-die package is developed for the miniaturization and integration of electronic devices. The developed package has a stacked flip-chip-on-chip structure and eight flip chips are arranged in four vertical layers using four silicon chip carriers with through silicon vias (TSVs). In each layer, two flip chips are mounted on the silicon chip carrier with 100 um solder bumps, and multiple TSVs are fabricated in each silicon chip carrier for underfill dispensing purpose. The 3D module with four stacked layers is sequentially assembled by the standard surface mount reflow process and finally mounted to a substrate. In the underfill process, conventional I-pass underfill is used to fill up the gaps of the bottom two layers as it has relatively fast spreading speed. For the top two chip carriers, underfill is dispensed through TSVs to fill the gaps. Unlike the conventional underfill process, the encapsulant in this case would not flow in the gaps by the capillary effect unless the dispensed materials can obtain enough kinetic energy to overcome the surface tension at the end of TSVs, and thus, smooth sidewall, proper dispensing settings and optimized TSV pattern are needed. After underfill, detailed inspections are performed to verify the quality of encapsulation. The results show that the combined I-pass/TSV underfill process gives void-free encapsulation and perfect fillets for the stacked 3D package.

Three-Dimensional (3D) Integration Technology

Three-dimensional (3D) integration and bumpless TSV (Through-Silicon-Via) technologies beyond post-scaling have been described. Since the extreme scaling is limited by physical and economic sense, 3D will be used concurrently with tow-dimensional legacy process. Because vertical wiring in WOW can be connected directly to the upper and lower substrates by self-alignment, bumps are not necessary when TSV interconnects are used. The low aspect ratio of TSVs allows a higher process margin and throughput in etching and metal filling. Multiple TSVs enable die-to-die connections independently, which improves the total yield in wafer-scale stacking. Stacking at the wafer level drastically increases the processing throughput, and bumpless multi-TSVs provide a yield equivalent to or greater than 2D scaling beyond 22-nm nodes.

Low-Power and Reliable Clock Network Design for Through-Silicon Via (TSV) Based 3D ICs

This paper focuses on low-power and low-slew clock network design and analysis for through-silicon via (TSV) based three-dimensional stacked ICs (3D ICs). First, we investigate the impact of the TSV count and the TSV resistance–capacitance (RC) parasitics on clock power consumption. Several techniques are introduced to reduce the clock power consumption and slew of the 3D clock distribution network. We analyze how these design factors affect the overall wire length, clock power, slew, and skew in 3D clock network design. Second, we develop a two-step 3D clock tree synthesis method: 1) 3D abstract tree generation based on the three-dimensional method of means and medians (3D-MMM) algorithm; 2) buffering and embedding based on the slew-aware deferred-merge buffering and embedding (sDMBE) algorithm. We also extend the 3D-MMM method (3D-MMM-ext) to determine the optimal number of TSVs to be used in the 3D clock tree so that the overall power consumption is minimized. Related SPICE simulation indicates that: 1) a 3D clock network that uses multiple TSVs significantly reduces the clock power compared with the single-TSV case, 2) as the TSV capacitance increases, the power savings of a multiple-TSV clock network decreases, and 3) our 3D-MMM-ext method finds a close-to-optimal design point in the “TSV count versus power consumption” tradeoff curve very efficiently.

Integration Aspects of the Implementation of Through Silicon Vias (TSV) for CMOS Image Sensors

One of the first device types to benefit from TSV implementation is the CMOS image sensor, an image capture device designed to combine high image quality within a compact form-factor that can be mass produced at low cost. End markets include mobile phones, PDAs and gaming consoles. STMicroelectronics is pioneering their production, based on ≤65nm CMOS technology, at its 300mm facility in Crolles. These sensors employ TSVs as part of a wafer level package allowing the camera module to be directly soldered to a phone PCB thereby saving cost, space and time to manufacture. SPTS's Versalis fxP system is being used to combine multiple TSV formation processes onto one platform including hard-mask deposition, hard-mask etching, TSV etching, partial PMD etching, dielectric liner deposition and spacer etching to define the area for the metal contact. All processes are carried out on a silicon wafer bonded to a glass carrier, through which the final device is illuminated. We will present a TSV silicon etch process for 70 μm x 70 μm Vias in a thinned 300mm silicon wafer on glass carriers with an etch rate uniformity of ≤±1% and sidewall scalloping in the range 80–210 nm. We will show that this process can be conveniently mixed in production with the various oxide etches. A PECVD dielectric liner deposited at &amp;lt;200 °C having excellent coverage, thermal stability and adhesion combined with a breakdown voltage &amp;gt;8 MVcm−1 and leakage current &amp;lt;1E-7 Acm−2 will also be described. Process integration aspects will be discussed using high resolution SEMS to show the key material interfaces in critical areas such as feature corners and along sidewalls. Furthermore the successful implementation of TSV technology on ST's CMOS image sensors will be demonstrated through a combination of electrical characteristics, parametric device data and overall device performance/reliability.