Multi-TSV and E-Field Sharing Aware Full-chip Extraction and Mitigation of TSV-to-Wire Coupling

Abstract

The through-silicon-via (TSV) introduces new parasitic components into 3-D ICs. This paper presents a novel method of extracting the parasitic capacitance between TSVs and their surrounding wires. For the first time, we examine electrical field (E-field) sharing effects from multiple TSVs and neighboring wires and their impact on timing, power, and noise with full-chip sign-off analyses. For fast and accurate full-chip extraction, we propose a pattern-matching algorithm that accounts for the physical dimensions of multiple TSVs and neighboring wires and captures all E-field interactions. Compared with the average error of a field solver, that of our extraction method, which requires only 2.4 s runtime and negligible memory for a full-chip 64-point fast Fourier transform (FFT64) design with 330 TSVs, is 0.063fF. Upon extraction of TSV-related parasitics, we observe that TSV-to-wire capacitance significantly increase average TSV net noise and the longest path delay. To reduce TSV-to-wire coupling, we implement two full-chip optimization methods and show that increasing the minimum distance between TSVs and neighboring wires reduces both coupling noise and the aggressor count. Thanks to E-field sharing from grounded wire guard rings, victim TSVs are more effectively shielded from aggressor noise. A full-chip analysis shows that these methods are highly effective in reducing noise with only slight impact on timing and area.