Multiple Page Sizes Research Articles

TLB Coalescing for Multi-Grained Page Migration in Hybrid Memory Systems

Superpages have long been proposed to enlarge the coverage of translation lookaside buffer (TLB). They are extremely beneficial for reducing address translation overhead in big memory systems, such as hybrid memory systems that composed of DRAM and non-volatile memories (NVMs). However, superpages conflict with fine-grained memory migration, one of the key techniques in hybrid memory systems to improve performance and energy efficiency. Fine-grained page migrations usually require to splinter superpages, mitigating the benefit of TLB hardware for superpages. In this paper, we present Tamp, an efficient memory management mechanism to support multiple page sizes in hybrid memory systems. We manage large-capacity NVM using superpages, and use a relatively small size of DRAM to cache hot base pages within the superpages. We find that there are remarkable contiguity exist for hot base pages in superpages. In response, we bind those contiguous hot pages together and migrate them to DRAM. We also propose multi-grained TLBs to coalesce multiple page address translations into a single TLB entry. Our experimental results show that Tamp can significantly reduce TLB misses by 62.4% on average, and improve application performance (IPC) by 16.2%, compared to a page migration policy without TLB coalescing support.

Mosaic

Contemporary discrete GPUs support rich memory management features such as virtual memory and demand paging. These features simplify GPU programming by providing a virtual address space abstraction similar to CPUs and eliminating manual memory management, but they introduce high performance overheads during (1) address translation and (2) page faults. A GPU relies on high degrees of thread-level parallelism (TLP) to hide memory latency. Address translation can undermine TLP, as a single miss in the translation lookaside buffer (TLB) invokes an expensive serialized page table walk that often stalls multiple threads. Demand paging can also undermine TLP, as multiple threads often stall while they wait for an expensive data transfer over the system I/O (e.g., PCIe) bus when the GPU demands a page. In modern GPUs, we face a trade-off on how the page size used for memory management affects address translation and demand paging. The address translation overhead is lower when we employ a larger page size (e.g., 2MB large pages, compared with conventional 4KB base pages), which increases TLB coverage and thus reduces TLB misses. Conversely, the demand paging overhead is lower when we employ a smaller page size, which decreases the system I/O bus transfer latency. Support for multiple page sizes can help relax the page size trade-off so that address translation and demand paging optimizations work together synergistically. However, existing page coalescing (i.e., merging base pages into a large page) and splintering (i.e., splitting a large page into base pages) policies require costly base page migrations that undermine the benefits multiple page sizes provide. In this paper, we observe that GPGPU applications present an opportunity to support multiple page sizes without costly data migration, as the applications perform most of their memory allocation en masse (i.e., they allocate a large number of base pages at once).We show that this en masse allocation allows us to create intelligent memory allocation policies which ensure that base pages that are contiguous in virtual memory are allocated to contiguous physical memory pages. As a result, coalescing and splintering operations no longer need to migrate base pages.

Efficient Address Translation for Architectures with Multiple Page Sizes

Processors and operating systems (OSes) support multiple memory page sizes. Superpages increase Translation Lookaside Buffer (TLB) hits, while small pages provide fine-grained memory protection. Ideally, TLBs should perform well for any distribution of page sizes. In reality, set-associative TLBs -- used frequently for their energy efficiency compared to fully-associative TLBs -- cannot (easily) support multiple page sizes concurrently. Instead, commercial systems typically implement separate set-associative TLBs for different page sizes. This means that when superpages are allocated aggressively, TLB misses may, counter intuitively, increase even if entries for small pages remain unused (and vice-versa). We invent MIX TLBs, energy-frugal set-associative structures that concurrently support all page sizes by exploiting superpage allocation patterns. MIX TLBs boost the performance (often by 10-30%) of big-memory applications on native CPUs, virtualized CPUs, and GPUs. MIX TLBs are simple and require no OS or program changes.

Efficient Address Translation for Architectures with Multiple Page Sizes

Processors and operating systems (OSes) support multiple memory page sizes. Superpages increase Translation Lookaside Buffer (TLB) hits, while small pages provide fine-grained memory protection. Ideally, TLBs should perform well for any distribution of page sizes. In reality, set-associative TLBs -- used frequently for their energy efficiency compared to fully-associative TLBs -- cannot (easily) support multiple page sizes concurrently. Instead, commercial systems typically implement separate set-associative TLBs for different page sizes. This means that when superpages are allocated aggressively, TLB misses may, counter intuitively, increase even if entries for small pages remain unused (and vice-versa). We invent MIX TLBs, energy-frugal set-associative structures that concurrently support all page sizes by exploiting superpage allocation patterns. MIX TLBs boost the performance (often by 10-30%) of big-memory applications on native CPUs, virtualized CPUs, and GPUs. MIX TLBs are simple and require no OS or program changes.

Efficient Address Translation for Architectures with Multiple Page Sizes

Efficient Address Translation for Architectures with Multiple Page Sizes

NAND Flash Memory With Multiple Page Sizes for High-Performance Storage Devices

In recent years, the demand for NAND flash-based storage devices has rapidly increased because of the popularization of various portable devices. NAND flash memory (NFM) offers many advantages, such as nonvolatility, high performance, the small form factor, and low-power consumption, while achieving high chip integration with a specialized architecture for bulk data access. A unit of NFM’s read and program operations, the page, has continuously grown. Although increasing page size reduces costs, it adversely affects performance because of the resultant side effects, such as fragmentation and wasted space, caused by the incongruity of data and page sizes. To address this issue, we propose a multiple-page-size NFM architecture and its management. Our method dramatically improves write performance through adopting multiple page sizes without requiring additional area overhead or manufacturing processes. Based on the experimental results, the proposed NFM improves write latency and NFM lifetime by up to 65% and 62%, respectively, compared with the single-page-size NFM.

운영체제 도움 없이 멀티 페이지를 지원하는 저전력 TLB 구조

비록 멀티 페이지 TLB는 성능을 향상시키는데 효과적이지만, 운영체제의 도움을 통한 기존의 방법은 사용자 응용 프로그램에서는 멀티 페이지를 사용할 수 없는 치명적인 단점을 가진다. 이에 본 논문에서는 운영체제의 지원 없이 멀티 페이지를 이용하여 고성능과 저전력을 얻을 수 있는 새로운 멀티 TLB 구조를 제안한다. 제안된 TLB는 작은 페이지를 위한 TLB와 큰 페이지를 위한 TLB로 구성되며, 모두 완전연관 뱅크 구조를 가지고 있다. 작은 페이지를 지원하는 S-TLB(Small TLB)는 큰 페이지를 지원하는 L-TLB(Large TLB)에서 추출된 작은 페이지를 저장하게 되며, L-TLB는 CPU로부터 요청된 작은 페이지를 포함한 큰 가상 페이지 주소를 저장하게 된다. CPU가 요청한 가상주소의 특별한 한 비트와 두 비트를 이용하여 S-TLB와 L_TLB의 각각의 하나의 뱅크만이 접근되며, 동시에 접근되는 엔트리 수 감소에 의해 에너지 소비를 줄일 수 있다. 또한 본 논문에서 효과적인 성능향상을 위해 간단한 1비트 LRU 정책을 제안하였다. 제안된 LRU 정책은 각 TLB 엔트리에 추가적인 1 비트를 사용하여 최근에 참조된 블록을 나타낸다. 이 방법은 간단하게 L-TLB로부터 가장 최근에 참조된 페이지를 선택할 수 있다. 시뮬레이션 결과에 따르면, 제안된 구조는 완전연관 사상 TLB, Dual TLB 그리고 ARM TLB에 비해 76%, 57%, 그리고 6%의 에너지*지연시간을 줄일 수 있었다. Even though the multiple pages TLB are effective in improving the performance, a conventional method with OS support cannot utilize multiple page sizes in user application. Thus, we propose a new multiple-TLB structure supporting multiple page sizes for high performance and low power consumption without any operating system support. The proposed TLB is organised as two parts of a S-TLB(Small TLB) with a small page size and a L-TLB(Large TLB) with a large page size. Both are designed as fully associative bank structures. The S-TLB stores small pages are evicted from the L-TLB, and the L-TLB stores large pages including a small page generated by the CPU. Each one bank module of S-TLB and L-TLB can be selectively accessed base on particular one and two bits of the virtual address generated from CPU, respectively. Energy savings are achieved by reducing the number of entries accessed at a time. Also, this paper proposed the simple 1-bit LRU policy to improve the performance. The proposed LRU policy can present recently referenced block by using an additional one bit of each entry on TLBs. This method can simply select a least recently used page from the L-TLB. According to the simulation results, the proposed TLB can reduce Energy * Delay by about 76%, 57%, and 6% compared with a fully associative TLB, a ARM TLB, and a Dual TLB, respectively.

High performance set associative translation lookaside buffers for low power microprocessors

A fast low power four-way set-associative translation lookaside buffer (TLB) is proposed. The proposed TLB allows single clock phase accesses at clock frequencies above 1 GHz. Comparisons to a conventional fully associative CAM tagged TLB, which is the type most commonly used in embedded processors, with the same number of entries on a 65 nm low standby power process show that the proposed design has 28% lower delay and up to 50% lower energy delay product. Unlike previous set-associative TLBs, which replicate the TLB to support multiple page sizes, multiple page sizes are supported on a way-by-way basis. Alternative conventional CAM tagged and set-associative TLBs are investigated with regard to access latency, power dissipation and hit rates.

Effectiveness of multiple pageable page sizes for commercial applications

AbstractThis paper investigates the computational characteristics of the software applications that are developed to support typical modern e‐commerce applications. These applications have a significant impact on global commerce, and their influence is expected to continue. We show that the micro‐architectural features of the memory subsystem, assisted by the operating system (such as the use of concurrent pageable page sizes), can significantly improve the performance of these applications. In particular, we show that using 64 kB page size in addition to the default 4 kB page size provides substantial throughput improvements for a typical commercial application (Trade6) without adding any complexity for the application developer or the system administrator. Copyright © 2007 John Wiley & Sons, Ltd.

Concurrent support of multiple page sizes on a skewed associative TLB

Some architecture definitions (e.g., Alpha) allow the use of multiple virtual page sizes even for a single process. Unfortunately, on current set-associative TLBs (translation lookaside buffers), pages with different sizes cannot coexist together. Thus, processors supporting multiple page sizes implement fully associative TLBs. In this research note, we show how the skewed-associative TLB can accommodate the concurrent use of multiple page sizes within a single process. This allows us to envision either medium size L1 TLBs or very large L2 TLBs supporting multiple page sizes.

Dual TLB structure for supporting two page sizes

A new translation lookaside buffer (TLB) structure is proposed which supports dual page sizes so as to obtain the effect of multiple page sizes with high performance and at low cost without operating system support. According to the results of a comparison and analysis, a similar performance can be achieved by using fewer TLB entries compared with conventional TLBs.

Propeties of storage hierarchy systems with multiple page sizes and redundant data

The need for high performance, highly reliable storage for very large on-line databases, coupled with rapid advances in storage device technology, has made the study of generalized storage hierarchies an important area of research. This paper analyzes properties of a data storage hierarchy system specifically designed for handling very large on-line databases. To attain high performance and high reliability, the data storage hierarchy makes use of multiple page sizes in different storage levels and maintains multiple copies of the same information across the storage levels. Such a storage hierarchy system is currently being designed as part of the INFOPLEX database computer project. Previous studies of storage hierarchies have primarily focused on virtual memories for program storage and hierarchies with a single page size across all storage levels and/or a single copy of information in the hierarchy. In the INFOPLEX design, extensions to the least recently used (LRU) algorithm are used to manage the storage levels. The read-through technique is used to initially load a referenced page of the appropriate size into all storage levels above the one in which the page is found. Since each storage level is viewed as an extension of the immediate higher level, an overflow page from level i is always placed in level i + 1. Important properties of these algorithms are derived. It is shown that depending on the types of algorithms used and the relative sizes of the storage levels, it is not always possible to guarantee that the contents of a given storage level i is always a superset of the contents of its immediate higher storage level i - 1. The necessary and sufficient conditions for this property to hold are identified and proved. Furthermore, it is possible that increasing the size of intermediate storage levels may actually increase the number of references to lower storage levels, resulting in reduced performance. Conditions necessary to avoid such an anomaly are also identified and proved.