Multiple Instruction Research Articles

‘I worry about getting it wrong and looking like a silly billy’: does explicit classroom-based strategy intervention change pupils’ attitudes towards speaking in the modern foreign languages classroom?

ABSTRACT A number of factors among schoolchildren in England are currently contributing to poor attitudes towards speaking in the modern foreign languages (MFL) classroom. Although multiple explicit strategy-based instruction (SBI) intervention studies have appeared in recent years, very few studies have focused on its effect on oral skills and, in particular, pupils' attitudes towards speaking in the target language (TL). From the small pool of SBI investigations into schoolchildren whose first language (L1) is English, there is some evidence of success among boys in particular. The present quasi-experimental, two-cycle action research and development study of beginner (Year 7) and intermediate (Year 10) learners of L2 French (N = 148) investigated the impact of 12 hours of strategy intervention training on attitudes towards TL speaking skills in the MFL classroom in an all-boys selective secondary school in England. To assess the impact of the intervention, a mixed-methods approach was adopted; data were captured via questionnaires, lesson observations and interviews. In Cycle 2, pupils navigated the ‘Strategy Island Map', an innovative tool to track their strategy use when speaking in the TL. Results suggest that explicit SBI improved attitudes towards speaking among both age groups. Implications for practice and suggestions for future research are discussed.

WDBT: Non-volatile memory wear characterization and mitigation for DBT systems

Emerging high-capacity and byte-addressable non-volatile memory (NVM) is promising for the next-generation memory system. However, NVM suffers from limited write endurance, as an NVM cell will wear out very soon after a certain number of writes, making NVM undependable. To address this issue, many wear reduction and leveling mechanisms have been proposed. Nevertheless, most of these mechanisms are developed without the knowledge of application semantics and behaviors. In this paper, we advocate application-level wear management, which allows us to create effective and flexible wear reduction and leveling techniques for specific application domains. Particularly, we find that applications running with dynamic binary translation (DBT) exhibit significantly more writes. This is because DBT systems need to handle architectural differences when translating instructions across different architectures. In this paper, we present WDBT, which focuses on wear reduction and leveling for DBT systems on NVM. WDBT is designed based on common practices of DBT systems to reduce the majority of writes introduced by DBT. We also implement a prototype of WDBT using a real-world DBT system, QEMU, for multiple popular instruction sets. Experimental results on SPEC CPU 2017 show that WDBT can effectively reduce writes by 52.09% and 34.48% for x86-64 and RISC-V, respectively. Moreover, the performance overhead of WDBT is negligible.

Hardware Accelerators for Real-Time Face Recognition: A Survey

Real-time face recognition has been of great interest in the last decade due to its wide and variant critical applications which include biometrics, security in public places, and identification in login systems. This has encouraged researchers to design fast and accurate embedded and portable systems that are capable to detect and recognize a large number of faces at almost video frame rate. Due to the increasing volume of reference faces, traditional general purpose computing engines such as the ones based on Intel’s Pentium processors have shown not to be adequate and various dedicated hardware accelerators based on either Graphical Processing Unit (GPU), Field Programmable Gate Arrays (FPGA), Application Specific Integrated Circuit (ASIC), or even multi-core Central Processing Units (CPU) have emerged. Earlier published review papers on face detection/recognition have discussed face detection and face recognition algorithms enhancement that improve the detection accuracy. Nevertheless, none of them has reviewed the hardware accelerators used for this application. Accordingly, this paper aims to provide a comprehensive review of the most recent face recognition algorithms and associated embedded hardware systems targeting real-time performance. A detailed comparison between neural network and non-neural network-based algorithms in terms of accuracy and processing time is provided. Discussions on their suitability to be implemented into parallel hardware architectures such as Single Instruction Multiple Thread (SIMT) or Single Instruction Multiple Data (SIMD) is also discussed.

Fifty years of microprocessor evolution: from single CPU to multicore and manycore systems

Nowadays microprocessors are among the most complex electronic systems that man has ever designed. One small silicon chip can contain the complete processor, large memory and logic needed to connect it to the input-output devices. The performance of today's processors implemented on a single chip surpasses the performance of a room-sized supercomputer from just 50 years ago, which cost over $ 10 million [1]. Even the embedded processors found in everyday devices such as mobile phones are far more powerful than computer developers once imagined. The main components of a modern microprocessor are a number of general-purpose cores, a graphics processing unit, a shared cache, memory and input-output interface and a network on a chip to interconnect all these components [2]. The speed of the microprocessor is determined by its clock frequency and cannot exceed a certain limit. Namely, as the frequency increases, the power dissipation increases too, and consequently the amount of heating becomes critical. So, silicon manufacturers decided to design new processor architecture, called multicore processors [3]. With aim to increase performance and efficiency these multiple cores execute multiple instructions simultaneously. In this way, the amount of parallel computing or parallelism is increased [4]. In spite of mentioned advantages, numerous challenges must be addressed carefully when more cores and parallelism are used. This paper presents a review of microprocessor microarchitectures, discussing their generations over the past 50 years. Then, it describes the currently used implementations of the microarchitecture of modern microprocessors, pointing out the specifics of parallel computing in heterogeneous microprocessor systems. To use efficiently the possibility of multi-core technology, software applications must be multithreaded. The program execution must be distributed among the multi-core processors so they can operate simultaneously. To use multi-threading, it is imperative for programmer to understand the basic principles of parallel computing and parallel hardware. Finally, the paper provides details how to implement hardware parallelism in multicore systems.

Coded Websites vs Wordpress Websites

This document gives multiple instructions related to web developers using older as well as newer technology. Websites are being created using newer technologies like wordpress whereas on the other hand many people prefer making websites using the traditional way. This document will clear the doubt whether an individual should use wordpress websites or coded websites according to the users convenience. The Responsiveness of the websites, the use of CMS nowadays, more and more up gradation of technologies with SEO, themes, templates, etc. make things like web development much much easier. The aesthetics, the culture, the expressions, the features all together add up in order make the designing and development a lot more efficient and effective. Digital Marketing has a tremendous growth over the last two years and yet shows no signs of stopping, is closely related with the web development environment. Nowadays all businesses are going online due to which the impact of web development has become such that it has become an integral part of any online business.

Design of Low Power Cam Memory Cell for the Next Generation Network Processors

In the modern world, high performance embedded applications in the field of multimedia, networking, and imaging are increasing day by day. These applications require high performance and more complex out-of-order superscalar processor. These complex dynamic instructions scheduling superscalar processors need higher levels of on-chip integration designs which are often associated with power dissipation. These out-of-order superscalar processors achieve higher performance compared to other processors by simultaneous fetching, decoding and execution for multiple instructions in out-of-order that are used in the next generation network processors. The main data path resources of the processor use CAM+RAM structure which is the major power consuming unit in the overall out-of-order processor design. The proposed new design of CAM+RAM with power-gating technique reduces the overall average power consumption compared to the conventional design without any significant impact on their performance.

Co-Creating Learning in Oceanography

Using active methods to involve students in teaching improves student learning (Deslauriers et al., 2011, 2019; Freeman et al., 2014). For many teachers, breaking up a lecture with multiple choice questions and peer instruction has become an integral part of their teaching (Stains et al., 2018). We suggest involving students in creating the framework in which they learn together with their teachers (Cook-Sather et al., 2014; Bovill, 2020). Teaching then becomes more inclusive, and students try out new roles that support them in becoming more independent, secure, and responsible (Bovill, 2020). Co-creation gives students the chance to feel competent both in class and in their lives, as formative interactions make taught content more relevant to them (Boston, 2002; Black and William, 2009). Experiencing competency, autonomy, and relatedness is what makes intrinsic motivation possible (Deci and Ryan, 2000). It is thus not surprising that co-creation enhances learning and leads to more positive interactions between students and teachers (Bovill, 2020; Kaur and Noman, 2020).

Advances in parallel and distributed computing and its applications

Advances in parallel and distributed computing and its applications

Design and Assertion Based Verification of RISC-V Processor Subsystems

RISC-V is an open, free standard architecture. As its open-source architecture, it can be used in multiple applications like embedded processors, IoT, artificial intelligence, machine learning, military and defense applications. The parameters like throughput, performance, high speed etc., become essential in designing processor architecture. Pipelining is one such unique feature supported by RISC-V ISA, which basically involves the execution of multiple instructions in single cycle. This feature helps in improving the performance of the processor architecture. RISC-V ISA supports five stages of pipelining they are instruction fetch, instruction decode, execute, memory and write-back stage. The work covered in this paper involves the design and implementation of the subsystems of the RISC-V ISA which are present in different stages of pipeline architecture. The subsystems included in this work are Floating Point Unit (FPU) of Execute stage, Branch Prediction Unit (BPU) of instruction fetch stage, Forwarding Unit of execution stage, Operand Logic of decode stage and Floating-Point register file of Write-back stage. These subsystems are designed using Verilog Hardware Description Language in Xilinx ISE. Followed by the implementation the verification of the floating-point unit and the forwarding unit is performed using System Verilog Assertions in QuestaSim. The Assertion coverage report for the same is extracted.

Quality and Educational Value of Publicly Accessible Procedural Videos on Endovascular Repair of Abdominal Aortic Aneurysms

YouTube is the most popular platform among surgical trainees to find audiovisual resources; however, the quality and educational value of its contents are poorly understood. Endovascular aneurysm repair (EVAR) of abdominal aortic aneurysms (AAAs) is a common procedure with multiple different graft designs and deployment instructions for which videos are frequently accessed to learn or refresh these techniques. We assessed the content and quality of the current videos for EVAR on YouTube.

On the performance investigation of a fast optical switches based optical high performance computing infrastructure

Optical networks based on fast optical switches (FOSes) could potentially solve the latency, bandwidth, cost and power consumption challenges in current electrical switches (ESes) based high performance computing (HPC) networks. In this work, we present a novel HPC network which employs distributed FOS interconnecting by removing ES (Firefly). In Firefly, Dragonfly topology is adopted for the inter-group connection of blades, while the intra-group connection of blades is implemented by FOS with fast optical flow control. The Firefly exploits the wavelength, space, and time switching domain with nanoseconds reconfiguration time of the FOS to achieve efficient statistical multiplexing operation. We numerically investigate the Firefly performance with real HPC traffic traces collected by running multiple computing applications in MareNostrum 3 HPC infrastructure with Leaf-Spine architecture. Compared with Leaf Spine architecture, results show that Firefly performs 62.4%, 54%, 68.6%, and 71.8% less latency for the applications Conjugate Gradient (CG), Multi-Grid (MG), Multiple Instruction Lattice Computation (MILC), and Miniature Molecular Dynamics (MINI_MD), respectively. Moreover, Firefly can save 56.4% cost and 65.7% power consumption, respectively, with respect to Leaf-Spine when both support around 10,000 blades.

Instrument Set Decontamination Workflows Designed for Success in Sterile Processing

In sterile processing, several factors can result in confusion and unpredictable quality outcomes in surgical instrument sets, including the large number of instruments to manage, the complexity of certain instruments, and the multiple instructions for cleaning solutions and cleaning equipment for use. At a multihospital health system, the director of sterile processing had a vision that involved designing standard decontamination workflows and standardized cleaning pathways based on quality concepts to support patient safety. When there was a pause in elective surgeries in the spring of 2020 as a result of the spread of coronavirus disease 2019, sterile processing personnel became available to participate in a project to create and test these new standardized cleaning pathways and decontamination workflows. This article provides an overview of the inception and execution of this project and how instrument cleaning and decontamination was streamlined to promote a more efficient workflow for sterile processing.

PZLAST: an ultra-fast amino acid sequence similarity search server against public metagenomes.

Summary: Similarity searches of amino acid sequences against the public metagenomic data can provide users insights about the function of sequences based on the environmental distribution of similar sequences. However, a considerable reduction in the amount of data or the accuracy of the result was necessary to conduct sequence similarity searches against public metagenomic data, because of the vast data size more than Terabytes. Here, we present an ultra-fast service for the highly accurate amino acid sequence similarity search, called PZLAST, which can search the user’s amino acid sequences to several Terabytes of public metagenomic sequences in ∼10–20 min. PZLAST accomplishes its search speed by using PEZY-SC2, which is a Multiple Instruction Multiple Data many-core processor. Results of PZLAST are summarized by the ontology-based environmental distribution of similar sequences. PZLAST can be used to predict the function of sequences and mine for homologs of functionally important gene sequences.Availability and implementationPZLAST is freely accessible at https://pzlast.riken.jp/meta without requiring registration.Supplementary information Supplementary data are available at Bioinformatics online.

MULTIPLE INTELLIGENCES OF UNDERACHIEVERS AND OVERACHIEVERS IN SECONDARY SCHOOL ENGLISH

Underachievement as a phenomenon among school students exists in all subjects,but it is more pronounced in English, especially among students whose medium of learning is vernacular.The multiple intelligences-based instruction has been suggested as a remedy for overcoming the achievement discrepancy in English among EFL learners.This requires understanding the multiple intelligences of underachievers in English in comparison with their overachieving counterparts. The study aims to compare underachievers and overachievers in English with respect to their multiple intelligences.The participants of the study consisted of 85 underachievers and 77 overachievers in English, separated statistically by employing regression method from a larger sample of 447 ninth grade students of Kerala. Data were collected by administering Multiple Intelligences Scale for Secondary School Students,developed by the investigator. Inferential analysis by employing independent sample t-test revealed that underachievers and overachievers in English differed significantly in their Verbal-linguistic intelligence, Visual-spatial intelligence, Intrapersonal intelligence, Interpersonal intelligence and Naturalistic intelligence. The overachievers excel the underachievers in all the five components of multiple intelligences.The underachievers and overachievers in English were found almost alike in their Logical-mathematical intelligence, Bodily-kinesthetic intelligence, Musical intelligence, Existential intelligence and Moral-ethical intelligence.

Ego-Resiliency and physically-disabled learners: The Implementation of a Multiple Intelligences Teaching Approach

Background: Gardner’s multiple intelligences (MI) theory offers great opportunities to improve the diverse abilities potential in disabled learners. The current study investigated the effect of the MI teaching approach on physically disabled learners’ MI and ego resiliency. Methods: The purposive sample included male and female participants aged 14 to 30 years at the Arseye-Talash Institute in Urmia, West Azerbaijan for students with disabilities. To gain a complete picture of the phenomenon, the study used self-report questionnaires and semi-structured interviews. The study utilized an experimental design that included 30 participants overall, with 10 participants in a control group and 20 participants in two experimental groups according to the multiple intelligences-based instructions (MIBI) they received: first language (Persian)-oriented MIBIs & second language (English)-oriented MIBIs. For both experimental groups (n = 20), active and passive intelligences of the students were identified using a MI test. Then, the instruction was tailored to designing tasks to activate the passive intelligence for both groups. The control group (n = 10) received no training. The data were analyzed in SPSS software using ANOVA and Tukey’s post hoc HSD test. Results: Findings indicated that the use of the MI-based teaching approach contributed to a significant improvement in the learners’ MI (P <0.01) and ego resiliency (P <0.01). Furthermore, findings showed a positive impact of L2-oriented (English) MIBIs compared with L1-oriented (Persian) MIBI on physically disabled learners’ ego resiliency (P <0.01); however, no significant difference was found between the two languages’ MIBIs (P >0.01). Conclusion: The more diverse a learner’s experience, the more effective their learning will be, and accordingly, the more successful they will be in a world of challenges. This holds especially true for physically disabled learners who have diverse experiences and hence diverse learning needs.

Dynamic issue queue capping for simultaneous multithreaded processors

A simultaneous multithreaded (SMT) processor mixes multiple instruction streams in its superscalar out-of-order execution core for higher throughput. To achieve this, a superscalar processor is modified in such a way that someof its resources are duplicated and the rest is shared among multiple threads. The issue queue (IQ), which holds allwaiting instructions until they become ready and scheduled for execution, is among these shared resources. A baselineunmanaged IQ can give an unexpectedly low performance since a hungry thread can tie up most of the IQ entries.This type of scenario is also worse in terms of the fairness metric since some of the threads may experience starvation.Earlier studies propose both static and a limited type of dynamic capping of the IQ entries for regulating IQ traffic andproviding better SMT throughput and fairness. In this study, we propose an e?iciency-based dynamic capping (EDC)algorithm that calculates an efficiency metric for each thread and allocates the IQ entries for maximizing the throughputand the fairness metrics. EDC gives 3.6% better throughput and 3.9% better fairness results compared to the currentstate-of-the-art algorithms, on the average.

Inclusion Matters! Strategies For Improving Reading And Test Skills Of Special Education Students

The purpose of this quantitative retrospective quasi-experimental study was to determine if there was a statistically significant difference between sixth, seventh, and eighth-grade classrooms filled with both general education and special education students (mild to moderate disability) receiving multiple instructional strategies and sixth, seventh, and eighth-grade classrooms filled with general education students receiving only traditional instructional strategies. Students scoring 800 or above met reading standards for the year. Results of the analysis indicated students receiving traditional instructional strategies achieved a mean score of 830. The inclusion students receiving multiple instruction interventions also showed grade-level reading proficiency on the standardized test with a mean score of 818. The researcher focused on the issue to show there are positive outcomes from implementing inclusion. Recommendations involving a reading intervention such as guided reading groups, backwards design planning, and collaborative instruction were noted. A one-way Analysis of Variance (ANOVA) analysis tested significance and two-way ANOVA tested interaction. Both analyses were set at the.05 significance level to interpret the data. Keywords: Special education, General education, Disabilities, Inclusion, CRCT, Standardized Reading Tests.

Observação de pareamento de estímulos e instrução com múltiplos exemplares: efeitos sobre respostas de ouvinte e falante de crianças com TEA

Dois procedimentos têm sido propostos como alternativas para induzir repertórios não ensinados diretamente: 1) instrução com múltiplos exemplares (MEI); e 2) observação de pareamento de estímulos (SPOP). O MEI implica a rotação do ensino de diferentes respostas a um estímulo (ex. tato e resposta de ouvinte), o que favorece a aprendizagem incidental dessas respostas para novos estímulos a partir do ensino de apenas um dos tipos. No SPOP é exigida apenas a observação de estímulos apresentados contíguos, sem reforçamento diferencial para qualquer resposta. Os resultados de alguns estudos sugerem que uma maior frequência de pareamentos poderia levar a emergência de respostas de tato e ouvinte não ensinadas diretamente e que o pareamento de estímulos pode afetar o procedimento de MEI. O presente estudo avaliou o efeito de SPOP com uma frequência maior de pareamentos por tentativas sobre a emergência de respostas de tato e ouvinte em três crianças com Transtorno do Espectro Autista, e o efeito do SPOP no ensino dessas respostas por meio de MEI. Para dois participantes, o SPOP com mais pareamentos a cada tentativa favoreceu a emergência do repertório de ouvinte. Estes participantes somente aprenderam respostas de tato após o MEI. O SPOP teve um efeito facilitador no treino de MEI. Discute-se o papel do MEI e de treino de tato intensivo na emergência de repertórios de tato e ouvinte, assim como os tipos de controle de estímulo que o SPOP parece favorecer, e a possibilidade de investigar o SPOP em ambientes menos estruturados.

Brief Report: Using Computer-Assisted Multiple Exemplar Instruction to Facilitate the Development of Bidirectional Naming for Children with Autism Spectrum Disorder.

Bidirectional naming is an important ability which enables children to acquire listener and speaker behaviors through exposure to relevant word-object associations. Many children with autism spectrum disorder (ASD) or developmental delays do not demonstrate this ability and require systematic instruction. The purpose of the present study was to evaluate the efficacy of computer-assisted multiple exemplar instruction to facilitate bidirectional naming. Three 5-year-old Chinese boys with ASD participated in a multiple probe across three participants design. The results indicated that all three children's naming performance increased from pretest to posttest, supporting the potential practicality of the instructional system for use in applied settings.

Conceptual Modeling for Computer Organization and Architecture

Understanding computer system hardware, including how computers operate, is essential for undergraduate students in computer engineering and science. Literature shows students learning computer organization and assembly language often find fundamental concepts difficult to comprehend within the topic materials. Tools have been introduced to improve students comprehension of the interaction between computer architecture, assembly language, and the operating system. One such tool is the Little Man Computer (LMC) model that operates in a way similar to a computer but that is easier to understand. Even though LMC does not have modern CPUs with multiple cores nor executes multiple instructions, it nevertheless shows the basic principles of the von Neumann architecture. LMC aims to introduce students to such concepts as code and instruction sets. In this paper, LMC is used for an additional purpose: a tool with which to experiment using a new modeling language (i.e., a thinging machine; TM) in the area of computer organization and architecture without involving complexity in the subject. That is, the simplicity of LMC facilitates the application of TM without going deep into computer organization/architecture materials. Accordingly, the paper (a) provides a new way for using the LMC model for whatever purpose (e.g., education) and (b) demonstrates that TM can be used to build an abstract level of description in the organization/architect field. The resultant schematics from the TM model of LMC offer an initial case study that supports our thesis that TM is a viable method for hardware/software-independent descriptions in the computer organization and architect field of study.