Instruction Stream Multiple Data Research Articles

A massively parallel implicit 3D unstructured grid solver for computing turbulent flows on latest distributed memory computational architectures

An implicit unstructured grid density-based solver–PRAVAHA based on a parallel variant of the lower upper symmetric Gauss-Seidel (LUSGS) method is developed to compute large-scale engineering problems. A four-layered parallel algorithm is designed to efficiently compute three-dimensional turbulent flows on massively parallel modern multiple instruction multiple data-stream (MIMD) computational hardware. This data parallel approach achieves multiple layers of parallelism including continuity of flow solution, transfer of solution gradients, and calculation of drag/lift/solution residuals, right up to the innermost implicit LUSGS solver sub-routine, which is relatively less explored in the literature. Domain decomposition is performed using the METIS software based on multi-level graph partitioning algorithms. Non-blocking message-passing interface library functions are used to manage inter-processor communication through explicit message passing, efficiently. Super-linear scalability of the parallel solver is established on the current state-of-the-art supercomputing facility, the 838 teraflops PARAM seva on up to 6144 cores. Linear or even super-linear speedup on problems of significant size is observed even on ad-hoc parallel computing platforms like workstations and multi-node clusters, for turbulent flow simulations.

IMPROVING PARALLEL SOLUTIONS FOR METHOD OF LINES TO 1-D HEAT EQUATION BY USING FIVE POINT FINITE DIFFERENE

The aim of the study is to explain the numerical solutions of the one dimensional (1-D) of heat by using method of lines (MOLs). In the (MOLs) the derivative is firstly transformed to equivalent 5 point central finite differences methods (FDM) that is also transformed to the ordinary differential equations (ODEs). The produced (ODEs) systems are solved by the well-known techniques method of ODEs such as the 4th Runge - Kutta method and Runge - Kutta Fehlberg. And since of the conversion of the second derivative to the equivalent of the 5 points FDM which led to an increase in the size of the system equations ODEs, and thus increased we have improved the performance of these (MOLs) techniques by introduce parallel processing to speed up the solution of the produced ODE systems. The developed parallel technique, are suitable for running on MIMD (Multiple Instruction Stream, Multiple Data Stream) computers.

Parallel discontinuous Galerkin finite element method for computing hyperbolic conservation law on unstructured meshes

PurposeThe discontinuous Galerkin finite element method (DGFEM) is very suited for realizing high order resolution approximations on unstructured grids for calculating the hyperbolic conservation law. However, it requires a significant amount of computing resources. Therefore, this paper aims to investigate how to solve the Euler equations in parallel systems and improve the parallel performance.Design/methodology/approachDiscontinuous Galerkin discretization is used for the compressible inviscid Euler equations. The multi-level domain decomposition strategy was used to deal with the computational grids and ensure the calculation load balancing. The total variation diminishing (TVD) Runge–Kutta (RK) scheme coupled with the multigrid strategy was employed to further improve parallel efficiency. Moreover, the Newton Block Gauss–Seidel (GS) method was adopted to accelerate convergence and improve the iteration efficiency.FindingsNumerical experiments were implemented for the compressible inviscid flow problems around NACA0012 airfoil, over M6 wing and DLR-F6 configuration. The parallel acceleration is near to a linear convergence. The results indicate that the present parallel algorithm can reduce computational time significantly and allocate memory reasonably, which has high parallel efficiency and speedup, and it is well-suited to large-scale scientific computational problems on multiple instruction stream multiple data stream model.Originality/valueThe parallel DGFEM coupled with TVD RK and the Newton Block GS methods was presented for hyperbolic conservation law on unstructured meshes.

How General-Purpose can a GPU be?

The use of graphics processing units (GPUs) in general-purpose computation (GPGPU) is a growing field. GPU instruction sets, while implementing a graphics pipeline, draw from a range of single instruction multiple datastream (SIMD) architectures characteristic of the heyday of supercomputers. Yet only one of these SIMD instruction sets has been of application on a wide enough range of problems to survive the era when the full range of supercomputer design variants was being explored: vector instructions.
 
 This paper proposes a reconceptualization of the GPU as a multicore design with minimal exotic modes of parallelism so as to make GPGPU truly general.

A Survey of Paradigms for Building and Designing Parallel Computing Machines

In this paper we describe paradigms for building and designing parallel computing machines. Firstly we elaborate the uniqueness of MIMD model for the execution of diverse applications. Then we compare the General Purpose Architecture of Parallel Computers with Special Purpose Architecture of Parallel Computers in terms of cost, throughput and efficiency. Then we describe how Parallel Computer Architecture employs parallelism and concurrency through pipelining. Since Pipelining improves the performance of a machine by dividing an instruction into a number of stages, therefore we describe how the performance of a vector processor is enhanced by employing multi pipelining among its processing elements. Also we have elaborated the RISC architecture and Pipelining in RISC machines After comparing RISC computers with CISC computers we observe that although the high speed of RISC computers is very desirable but the significance of speed of a computer is dependent on implementation strategies. Only CPU clock speed is not the only parameter to move the system software from CISC to RISC computers but the other parameters should also be considered like instruction size or format, addressing modes, complexity of instructions and machine cycles required by instructions. Considering all parameters will give performance gain . We discuss Multiprocessor and Data Flow Machines in a concise manner. Then we discuss three SIMD (Single Instruction stream Multiple Data stream) machines which are DEC/MasPar MP-1, Systolic Processors and Wavefront array Processors. The DEC/MasPar MP-1 is a massively parallel SIMD array processor. A wide variety of number representations and arithmetic systems for computers can be implemented easily on the DEC/MasPar MP-1 system. The principal advantages of using such 64×64 SIMD array of 4-bit processors for the implementation of a computer arithmetic laboratory arise out of its flexibility. After comparison of Systolic Processors with Wave front Processors we found that both of the Systolic Processors and Wave front Processors are fast and implemented in VLSI. The major drawback of Systolic Processors is the problem of availability of inputs when clock ticks because of propagation delays in connection buses. The Wave front Processors combine the Systolic Processor architecture with Data Flow machine architecture. Although the Wave front processors use asynchronous data flow computing structure, the timing in the interconnection buses, at input and at output is not problematic..

An Extended PRAM-NUMA Model of Computation for TCF Programming

The main problems with current multicore architectures are that they are difficult to program due to the asynchrony of the underlying model of computation and that the performance is weak with many parallel workloads due to architectural limitations. To address these problems we have introduced the Parallel Random Access Machine - Non Uniform Memory Access (PRAM-NUMA) model of computation that can be used to implement efficient shared memory computers for general purpose parallel applications with enough parallelism and yet support sequential and NUMA legacy code and avoid loss of performance in applications with low parallelism. While programming of computers making use of the PRAM-NUMA model is provably easy, there is still room for improvement since they make implementing time-shared multitasking expensive, sometimes replicate much of the execution unnecessarily, and force the programmer to use looping and conditional control primitives in the case the application parallelism does not match the hardware parallelism. Thick Control Flow (TCF) is a parallel programming model that does not provide a fixed number of threads like PRAM-NUMA but a number of control flows that have certain thickness that can vary according to needs of the application catching the best parts of the dynamicism and generality of the original unbounded PRAM model and simplicity of the Single Instruction Stream Multiple Data Streams (SIMD) model. In this paper we study the possibility to implement the TCF model on top of the PRAM-NUMA model and propose an extended PRAM-NUMA model that makes this straightforward. A number of variants of the extended model are identified and tied to existing execution models. Architectural implementation techniques and programming of the extended model and its variants are outlined and discussed with short examples.

A General CPL-AdS Methodology for Fixing Dynamic Parameters in Dual Environments

The algorithm of Continuous Point Location with Adaptive d-ary Search (CPL-AdS) strategy exhibits its efficiency in solving stochastic point location (SPL) problems. However, there is one bottleneck for this CPL-AdS strategy which is that, when the dimension of the feature, or the number of divided subintervals for each iteration, d is large, the decision table for elimination process is almost unavailable. On the other hand, the larger dimension of the features d can generally make this CPL-AdS strategy avoid oscillation and converge faster. This paper presents a generalized universal decision formula to solve this bottleneck problem. As a matter of fact, this decision formula has a wider usage beyond handling out this SPL problems, such as dealing with deterministic point location problems and searching data in Single Instruction Stream-Multiple Data Stream based on Concurrent Read and Exclusive Write parallel computer model. Meanwhile, we generalized the CPL-AdS strategy with an extending formula, which is capable of tracking an unknown dynamic parameter λ in both informative and deceptive environments. Furthermore, we employed different learning automata in the generalized CPL-AdS method to find out if faster learning algorithm will lead to better realization of the generalized CPL-AdS method. All of these aforementioned contributions are vitally important whether in theory or in practical applications. Finally, extensive experiments show that our proposed approaches are efficient and feasible.

A parallel algorithm for generating bicompatible elimination orderings of proper interval graphs

In this paper, we first show how a certain ordering of vertices, called bicompatible elimination ordering (BCO), of a proper interval graph can be used to solve efficiently several problems in proper interval graphs. We, then, propose an NC parallel algorithm (i.e., polylogarithmic-time employing a polynomial number of processors) in SIMD CRCW PRAM (Single Instruction Stream Multiple Data Stream Concurrent Read Concurrent Write Parallel Random Access Machine) model of parallel computation to compute a BCO of a proper interval graph. To the best of our knowledge, this is the first NC parallel algorithm to compute a BCO of a proper interval graph.

New Reconfigurable Memory Architecture for Parallel Image-Processing LSI with Three-Dimensional Structure

A reconfigurable memory network for a parallel image-processing LSI with a three-dimensional structure is proposed. The proposed memory network can be dynamically configured by changing the connections between processing elements (PEs) and memories in accordance with the required part of the stored image data. In addition, a specification of the data bandwidth between PEs and the proposed memory network can be changed in the synchronization with single instruction stream-multiple data stream (SIMD) and multiple instruction stream-multiple data stream (MIMD) operations. Therefore, data transfer has greater flexibility. Also, from the result of the performance evaluation by implementation into the field programmable gate array (FPGA), it was successfully shown that the proposed memory network reduced the execution time by up to 28.2% for a 9×9 filtering operation.

A Fast Iterative Method for Eikonal Equations

In this paper we propose a novel computational technique to solve the Eikonal equation efficiently on parallel architectures. The proposed method manages the list of active nodes and iteratively updates the solutions on those nodes until they converge. Nodes are added to or removed from the list based on a convergence measure, but the management of this list does not entail an extra burden of expensive ordered data structures or special updating sequences. The proposed method has suboptimal worst-case performance but, in practice, on real and synthetic datasets, runs faster than guaranteed-optimal alternatives. Furthermore, the proposed method uses only local, synchronous updates and therefore has better cache coherency, is simple to implement, and scales efficiently on parallel architectures. This paper describes the method, proves its consistency, gives a performance analysis that compares the proposed method against the state-of-the-art Eikonal solvers, and describes the implementation on a single instruction multiple datastream (SIMD) parallel architecture.

Speedup bioinformatics applications on multicore-based processor using vectorizing and multithreading strategies.

Many computational intensive bioinformatics software, such as multiple sequence alignment, population structure analysis, etc., written in C/C++ are not multicore-aware. A multicore processor is an emerging CPU technology that combines two or more independent processors into a single package. The Single Instruction Multiple Data-stream (SIMD) paradigm is heavily utilized in this class of processors. Nevertheless, most popular compilers including Microsoft Visual C/C++ 6.0, x86 gnu C-compiler gcc do not automatically create SIMD code which can fully utilize the advancement of these processors. To harness the power of the new multicore architecture certain compiler techniques must be considered. This paper presents a generic compiling strategy to assist the compiler in improving the performance of bioinformatics applications written in C/C++. The proposed framework contains 2 main steps: multithreading and vectorizing strategies. After following the strategies, the application can achieve higher speedup by taking the advantage of multicore architecture technology. Due to the extremely fast interconnection networking among multiple cores, it is suggested that the proposed optimization could be more appropriate than making use of parallelization on a small cluster computer which has larger network latency and lower bandwidth.

실시간 Dense Disparity Map 추출을 위한 고성능 가속기 구조 설계

본 논문에서는 위상기반 양안스테레오정합 알고리즘을 이용, 실시간으로 dense disparity map을 추출 가능한 고성능 가속기 구조를 설계하였다. 채택된 알고리즘은 웨이블릿 기반의 위상차 기법의 강건성과 위상상관 기법의 기본적인 control 기법을 결합한 Local Weighted Phase Correlation(LWPC) 스테레오정합 알고리즘으로서 4개의 주요 단계로 구성이 되어 있다. 해당 알고리즘의 효율적인 병렬 하드웨어의 설계를 위하여, 제안된 가속기는 각 단계의 기능블록은 SIMD(Single Instruction Multiple Data Stream) 모드로 동작하게 되며, 전체적으로 각 기능 블록은 파이프라인(pipeline) 모드로 실행된다. 그 결과 제안된 구조에서 제시된 파이프라인 동작 모드의 선형 배열 프로세서는 행렬 순차수행 방법에 의한 2차원 영상처리에서 전치메모리의 필요를 제거하면서도 연산의 일반성과 고효율을 유지하게 한다. 제안된 하드웨어 구조는 Xilinx HDL을 이용하여 필요한 하드웨어 자원을 look up table, flip flop, slice, memory의 소모량으로 표현하였으며, 그 결과 실시간 처리 성능의 단일 칩 구현 가능성을 보여주었다. This paper proposes high performance coprocessor architecture for real time dense disparity computation based on a phase-based binocular stereo matching technique called local weighted phase-correlation(LWPC). The algorithm combines the robustness of wavelet based phase difference methods and the basic control strategy of phase correlation methods, which consists of 4 stages. For parallel and efficient hardware implementation, the proposed architecture employs SIMD(Single Instruction Multiple Data Stream) architecture for each functional stage and all stages work on pipelined mode. Such that the newly devised pipelined linear array processor is optimized for the case of row-column image processing eliminating the need for transposed memory while preserving generality and high throughput. The proposed architecture is implemented with Xilinx HDL tool and the required hardware resources are calculated in terms of look up tables, flip flops, slices, and the amount of memory. The result shows the possibility that the proposed architecture can be integrated into one chip while maintaining the processing speed at video rate.

A Reconfigurable Computing Processor Core for Multimedia System-on-Chip Applications

In this paper, a reconfigurable computing processor core for multimedia system-on-chip (SOC) applications is proposed. The reconfigurable computing processor comprises two-way single instruction stream multiple data stream (SIMD) based function units, flexible interconnection networks, two instruction caches, and two data caches. Every function units receives the instructions to perform three pipelining stages of operations to increase the throughput rate. With flexible interconnection networks and re-configurability, the reconfigurable computing processor core can not only perform 8-, 16-, 32-, and 64-bit simple operations but also perform some complex operations. In addition, the very large scale integration (VLSI) architecture has been implemented in 0.18 µm complementary metal oxide semiconductor (CMOS) process. Because of these features, the proposed reconfigurable architecture offers a feasible solution for multimedia SOC applications.

A low-cost media-processor based real-time MPEG-4 video decoder

Due to the high-sped development in semiconductor technology, general-purpose computers can process digital video, audio and graphics easily. Nowadays, the similar functionality has shifted from the general-purpose computer to the so-called media-processor one. Since the processor is targeted on mass-produced consumer electronic devices, the price and the ease of use are the main concern. The latest MPEG-4 video coding standard, which consumes relatively low bit-rate but yields acceptable quality, meets the target exactly. In this paper, by realizing an MPEG-4 codec using both general-purpose processor and media-processor, we investigated some issues related to the use of a media-processor for satisfying various multimedia compression and processing requirements. The investigated issues include the speedup of the MPEG-4 decoder based on a media-processor DSP chip, a multimedia co-processor or hardware accelerator, the very long instruction word (VLIW) and the single instruction multiple data stream (SIMD) programming techniques. Moreover, a media-processor based MPEG-4 solution for set-top box application is also included.

Vessel extraction in medical images by wave-propagation and traceback

This paper presents an approach for the extraction of vasculature from angiography images by using a wave propagation and traceback mechanism. We discuss both the theory and the implementation of the approach. Using a dual-sigmoidal filter, we label each pixel in an angiogram with the likelihood that it is within a vessel. Representing the reciprocal of this likelihood image as an array of refractive indexes, we propagate a digital wave through the image from the base of the vascular tree. This wave "washes" over the vasculature, ignoring local noise perturbations. The extraction of the vasculature becomes that of tracing the wave along the local normals to the waveform. While the approach is inherently single instruction stream multiple data stream (SIMD), we present an efficient sequential algorithm for the wave propagation and discuss the traceback algorithm. We demonstrate the effectiveness of our integer image neighborhood-based algorithm and its robustness to image noise.

Optimization of H.263 video encoding using a single processor computer: performance tradeoffs and benchmarking

We present the optimization and performance evaluation of a software-based H.263 video encoder. The objective is to maximize the encoding rate without losing the picture quality on an ordinary single processor computer such as a PC or a workstation. This requires optimization at all design and implementation phases, including algorithmic enhancements, efficient implementations of all encoding modules, and taking advantage of certain architectural features of the machine. We design efficient algorithms for DCT and fast motion estimation, and exploit various techniques to speed up the processing, including a number of compiler optimizations and removal of redundant operations. For exploiting the architectural features of the machine, we make use of low-level machine primitives such as Sun UltraSPARC's visual instruction set and Intel's multimedia extension, which accelerate the computation in a single instruction stream multiple data stream fashion. Extensive benchmarking is carried out on three platforms: a 167-MHz Sun UltraSPARC-1 workstation, a 233-MHz Pentium II PC, and a 600-MHz Pentium III PC. We examine the effect of each type of optimization for every coding mode of H.263, highlighting the tradeoffs between quality and complexity. The results also allow us to make an interesting comparison between the workstation and the PCs. The encoder yields 45.68 frames per second (frames/s) on the Pentium III PC, 18.13 frames/s on the Pentium II PC, and 12.17 frames/s on the workstation for QCIF resolution video with high perceptual quality at reasonable bit rates, which are sufficient for most of the general switched telephone networks based video telephony applications. The paper concludes by suggesting optimum coding options.

Parallel processing for a discrete element program

Abstract Reconfiguration of a discrete element code for parallel operation provided the opportunity to compare processing speeds on various hardware platforms. The program employed in this comparison, NURBM3DP, is a three dimensional, distinct element code employed to calculate dynamic response of a cavern in a jointed rock mass. On a 16 processor IBM SP2, it is capable of calculating dynamic response with 1000's of explicit time steps of jointed rock masses with up to 2,000,000 blocks. Comparison of single instruction multiple data stream (SIMD) and multiple-instruction multiple-data stream (MIMD) operation showed MIMD processing to provide the best overall parallelization. The full report of the comparisons of operation on different hardware with different data streaming configurations can be found at the research section of the Northwestern University Computational Mechanics site: http://www.tam.nwu.edu/compmech.html. In addition, a color movie of dynamic response of a million block model of a cavern responding to dynamic excitation can be seen at: http://geotech.civen.okstate.edu/ejge/ppr9801/index.htm.

Extensions to permutation warping for parallel volume rendering

Biomedical volume visualization requires high quality and high performance, but the existing high performance solutions such as the Shear Warp algorithm, 3D texture mapping, and special purpose hardware have problems. Permutation warping achieves high fidelity for biomedical datasets of regular rectilinear volumes, using a one-to-one communication scheme for optimal O(1) communication on massively parallel computers. Extensions are presented including data dependent optimizations using octrees, arbitrary view angle flexibility, and multiple instruction stream multiple data stream (MIMD) implementation. A MasPar MP-2, single instruction stream multiple data stream (SIMD) (16,384 processor), implementation achieves 14 frames/s, using trilinear reconstruction on 128 3 volumes for 400% runtime improvement over our previous result. A Proteus MIMD (32 processor) implementation achieves 1 frame/s on the same data. Additionally the PermWeb software architecture is presented, that has been shown as a proof of concept means to provide wide shared access to a powerful centralized renderer. All of these improvements make permutation warping an effective solution for biomedial volume visualization.

A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessor for multimedia applications

We have designed a microprocessor that is based on a single instruction multiple data stream (SIMD) architecture. It features a two-way superscalar architecture for multimedia embedded systems that need to support especially MPEG2 video decoding/encoding and 3DCG image processing. This microprocessor meets all requirements of embedded systems, including (a) MPEG2 (MP@ML) decoding and graphic processing capabilities for three-dimensional images, (b) programming flexibility, and (c) low power consumption and low manufacturing cost. High performance was achieved by enhanced parallel processing capabilities while adopting a SIMD architecture and a two-way superscalar architecture. Programming flexibility was increased by providing 170 dedicated multimedia instructions. Low power consumption was achieved by utilizing advanced process technology and power-saving circuits. The processor supports a general-purpose RISC instruction set. This feature is important, as the processor will have to work as a controller of various target systems. The processor has been fabricated by 0.21-/spl mu/m CMOS four-metal technology on a 9.84/spl times/10.12 mm die. It performs 2.16 GOPS/720 MFLOPS at an operating frequency of 180 MHz, with a power consumption of 1.2 W and a power supply of 1.8 V.

Parallelization and load balancing of a comprehensive atmospheric chemistry transport model

Chemistry transport models are generally claimed to be well suited for massively parallel processing on distributed memory architectures since the arithmetic-to-communication ratio is usually high. However, this observation proves insufficient to account for an efficient parallel performance with increasing complexity of the model. The modeling of the local state of the atmosphere ensues very different branches of the modules' code and greater differences in the computational work load and, consequently, runtime of individual processors occur to a much larger extent during a time step than reported for meteorological models. Variable emissions, changes in actinic fluxes, and all processes associated with cloud modeling are highly variable in time and space and are identified to induce large load imbalances which severely affect the parallel efficiency. This is more so, when the model domain encompasses more heterogeneous meteorological or regional regimes, which impinge dissimilarly on simulations of atmospheric chemistry processes. These conditions hold for the EURAD model applied in this study, which covers the European continental scale as integration domain. Based on a master-worker configuration with a horizontal grid partitioning approach, a method is proposed where the integration domain of the individual processors is locally adjusted to accommodate for load imbalances. This ensures a minimal communication volume and data exchange only with the next neighbors. The interior boundary adjustments of the processors are combined with routine boundary exchange which is required each time step anyway. Two dynamic load balancing schemes were implemented and compared against a conventional equal area partition and a static load balancing scheme. The methods are devised for massively parallel distributed memory computers of both, Single and Multiple Instruction stream Multiple Data stream (SIMD, MIMD) types. A midsummer episode of highly elevated ozone concentrations over parts of Europe was taken as test case. The dynamic load balancing approaches were found to perform significantly better and reduce idle times of the processors considerably. The efficiency was raised from to 62% for a 128 processor configuration.