A Reconfigurable Computing Processor Core for Multimedia System-on-Chip Applications

Abstract

In this paper, a reconfigurable computing processor core for multimedia system-on-chip (SOC) applications is proposed. The reconfigurable computing processor comprises two-way single instruction stream multiple data stream (SIMD) based function units, flexible interconnection networks, two instruction caches, and two data caches. Every function units receives the instructions to perform three pipelining stages of operations to increase the throughput rate. With flexible interconnection networks and re-configurability, the reconfigurable computing processor core can not only perform 8-, 16-, 32-, and 64-bit simple operations but also perform some complex operations. In addition, the very large scale integration (VLSI) architecture has been implemented in 0.18 µm complementary metal oxide semiconductor (CMOS) process. Because of these features, the proposed reconfigurable architecture offers a feasible solution for multimedia SOC applications.