Multiple-input Floating-gate MOS Research Articles

A Flexible Artificial Spiking Photoreceptor Enabled by a Single VO2 Mott Memristor for the Spike-Based Electronic Retina.

The neuromorphic vision system that utilizes spikes as information carriers is crucial for the formation of spiking neural networks. Here, we present a bioinspired flexible artificial spiking photoreceptor (ASP), which is realized by using a single VO2 Mott memristor that can simultaneously sense and encode the stimulus light into spikes. The ASP has high spike-encoded photosensitivity and ultrawide photosensing range (405-808 nm) with good endurance (>7 × 107) and high flexibility (bending radius ∼5 mm). Then, we put forward an all-spike electronic retina architecture that comprises one layer of ASPs and one layer of artificial optical nerves (AONs) to process the spike information. Each AON consists of a single Mott memristor connected in series with a neuro-transistor that is a multiple-input floating-gate MOS transistor. Simulation results demonstrate that the all-spike electronic retina can successfully segment images with high Shannon entropy, thus laying the foundation for the development of a spike-based neuromorphic vision system.

Low-Voltage Diode-Less Rectifier Based on Fully Differential Difference Transconductance Amplifier

This paper presents a voltage-mode low-voltage low-power diode-less rectifier with only one active element, the fully differential difference transconductance amplifier (FDDTA). The multiple-input floating-gate MOS (FG-MOS) transistor is used to build the differential pairs of the FDDTA resulting in the reduced count of transistors, circuit simplicity and the capability to work under low-voltage supply with extended input voltage range. The rectifier was designed with 0.9[Formula: see text]V voltage supply and 8[Formula: see text][Formula: see text]W power consumption, hence it is suitable for wearable electronics and biomedical applications. The simulation results obtained from the Cadence platform using 0.18[Formula: see text][Formula: see text]m TSMC CMOS technology show good performances for the designed circuit.

Low-voltage linear transconductor and a memory current using the MIFGMOS Transistor

The aim of this article is to probe the advantages that the Multi-Input Floating Gate MOS (MIFGMOS) transistor has versus the conventional MOSFET transistor in order to design analogue circuits with low-voltage operation and good linearity. To show this, the design and implementation of both a voltage to current converter (VIC) cell and a memory current cell (MIC) using MIFGMOS transistors is presented. The development is based on mathematical and simulation analysis as well as experimental results. Both cells present good performance and linearity according to theoretical analysis with a supply voltage of 1.7 V and a power consumption of about 20 μW, despite the long channel technology. These characteristics could be very important in analogue and mixed signal applications requiring low supply voltage and low power consumption. The cells presented here can be part of a sample and hold circuit operating in current mode, but applications are not restricted. Additionally, a comparison between simulation and experimental results obtained when we tested five 3-input MIFGMOS transistors are included to show their properties and behavior.

Wide-linear-range subthreshold OTA for low-power, low-Voltage, and low-frequency applications

We propose a novel configuration of linearized subthreshold operational transconductance amplifier (OTA) for low-power, low-voltage, and low-frequency applications. By using multiple input floating-gate (MIFG) MOS devices and implementing a cubic-distortion-term-canceling technique, the linear range of the OTA is up to 1.1 Vpp under a 1.5-V supply for less than 1% of transconductance variation, according to testing results from a circuit designed in a double-poly, 0.8-/spl mu/m, CMOS process. The power consumption of the OTA remains below 1 /spl mu/W for biasing currents in the range between 1-200 nA. The offset voltage due to secondary effects (contributed by parasitic capacitances, errors and mismatches of parameters, charge entrapment, etc.) is of the order of a few ten millivolts, and can be canceled by adjusting biasing voltages of input MIFG MOS transistors.

On the design robustness of threshold logic gates using multi-input floating gate MOS transistors

In this paper, the design robustness of logic circuits implemented as threshold logic gates with multi-input floating gate transistors is analyzed. The parameter variations of the basic components, namely the coupling capacitances of the floating gate MOSFETs and the sensing circuits for obtaining full logic levels, are investigated separately using appropriate array test structures. It is found that the dominant mismatch originates from the input offset voltage variations of the sensing circuits. Methods are presented for estimating the yield of a given logic circuit from the measured parameter distributions. The estimations are verified with measured data of a multiplier cell and of the encoding logic in a parallel fingerprint sensor architecture. Considerations are given for robust design of circuits based on threshold logic gates that use floating gate transistors.

A pseudologarithmic rectifier using unbalanced bias MFMOS differential pairs

A pseudologarithmic rectifier using multi-input floating-gate MOS (MFMOS) transistors is presented in this paper. The rectifiers consist of unbalanced bias matched MFMOS transistor differential pairs. The transfer characteristics of each subrectifier are determined by an appropriate choice of transistor aspect ratio and capacitive input coupling ratio such that in the summation of the output currents from each rectifier stage, the overall transfer characteristics closely approximates that of a true logarithmic behavior. It is operable at low supply voltage (/spl plusmn/0.9 V) and has low temperature dependence. Measured dynamic range of 27 dB and 16.5 dB, with a corresponding logarithmic error of /spl plusmn/0.7 dB and /spl plusmn/0.35 dB, has been obtained for three-stage and two-stage pseudologarithmic rectifiers, respectively, at room temperature. The measured logarithmic error for the three-stage pseudologarithmic rectifier at 125/spl deg/C is /spl plusmn/1.05 dB which is an increase of /spl plusmn/0.35 dB over a 100/spl deg/C range.

Translinear circuits in subthreshold MOS

In this paper we provide an overview of translinear circuit design using MOS transistors operating in subthreshold region. We contrast the bipolar and MOS subthreshold characteristics and extend the translinear principle to the subthreshold MOS ohmic region through a drain/source current decomposition. A front/back-gate current decomposition is adopted; this facilitates the analysis of translinear loops, including multiple input floating gate MOS transistors. Circuit examples drawn from working systems designed and fabricated in standard digital CMOS oriented process are used as vehicles to illustrate key design considerations, systematic analysis procedures, and limitations imposed by the structure and physics of MOS transistors. Finally, we present the design of an analog VLSI “translinear system” with over 590,000 transistors in subthreshold CMOS. This performs phototransduction, amplification, edge enhancement and local gain control at the pixel level.

Translinear circuits using subthreshold floating-gate MOS transistors

We describe a family of current-mode circuits with multiple inputs and multiple outputs whose output currents are products and/or quotients of powers of the input currents. These circuits are made up of multipleinput floating-gate MOS (FGMOS) transistors operating in the subthreshold regime. The powers are set by capacitor ratios; hence, they can be quite accurate. We analyze the general family of such circuits and present experimental data from several members that we fabricated in a standard 2μm double-poly p-well process through MOSIS.

A novel multi-input floating-gate MOS four-quadrant analog multiplier

A novel four-quadrant analog multiplier using multi-input floating-gate MOS (MFMOS) transistors has been designed and fabricated using a 2-/spl mu/m double-poly double-metal P-well CMOS process. It is essentially based on the quarter-square technique which relies on the square-law characteristic of the MOS transistor in the saturation region. The multiplier is realized with only four MFMOS transistors and a current source. The input range is 100% of the supply voltage and accepts either differential, single-ended, or floating input signals. Measured nonlinearity and total harmonic distortion are 0.2% and 0.5%, respectively, under full scale input conditions. Input noise is 170 /spl mu/V (rms), giving a 95 dB input dynamic range. The power dissipation is 1.1 mW and bandwidth is 12 MHz. Second-order effects on the multiplier performance have also been analyzed.