Multiple Hardware Research Articles

Quantum Modular Adder over GF(2n − 1) without Saving the Final Carry

Addition is the most basic operation of computing based on a bit system. There are various addition algorithms considering multiple number systems and hardware, and studies for a more efficient addition are still ongoing. Quantum computing based on qubits as the information unit asks for the design of a new addition because it is, physically, wholly different from the existing frequency-based computing in which the minimum information unit is a bit. In this paper, we propose an efficient quantum circuit of modular addition, which reduces the number of gates and the depth. The proposed modular addition is for the Galois Field GF(2n−1), which is important as a finite field basis in various domains, such as cryptography. Its design principle was from the ripple carry addition (RCA) algorithm, which is the most widely used in existing computers. However, unlike conventional RCA, the storage of the final carry is not needed due to modifying existing diminished-1 modulo 2n−1 adders. Our proposed adder can produce modulo sum within the range 0,2n−2 by fewer qubits and less depth. For comparison, we analyzed the proposed quantum addition circuit over GF(2n−1) and the previous quantum modular addition circuit for the performance of the number of qubits, the number of gates, and the depth, and simulated it with IBM’s simulator ProjectQ.

PDKit: A data science toolkit for the digital assessment of Parkinson's Disease.

PDkit is an open source software toolkit supporting the collaborative development of novel methods of digital assessment for Parkinson's Disease, using symptom measurements captured continuously by wearables (passive monitoring) or by high-use-frequency smartphone apps (active monitoring). The goal of the toolkit is to help address the current lack of algorithmic and model transparency in this area by facilitating open sharing of standardised methods that allow the comparison of results across multiple centres and hardware variations. PDkit adopts the information-processing pipeline abstraction incorporating stages for data ingestion, quality of information augmentation, feature extraction, biomarker estimation and finally, scoring using standard clinical scales. Additionally, a dataflow programming framework is provided to support high performance computations. The practical use of PDkit is demonstrated in the context of the CUSSP clinical trial in the UK. The toolkit is implemented in the python programming language, the de facto standard for modern data science applications, and is widely available under the MIT license.

Radio Frequency Fingerprinting on the Edge

Deep learning methods have been very successful at radio frequency fingerprinting tasks, predicting the identity of transmitting devices with high accuracy. We study radio frequency fingerprinting deployments at resource-constrained edge devices. We use structured pruning to jointly train and sparsify neural networks tailored to edge hardware implementations. We compress convolutional layers by a <inline-formula><tex-math notation="LaTeX">$27.2\times$</tex-math></inline-formula> factor while incurring a negligible prediction accuracy decrease (less than 1 percent). We demonstrate the efficacy of our approach over multiple edge hardware platforms, including a Samsung Gallaxy S10 phone and a Xilinx-ZCU104 FPGA. Our method yields significant inference speedups, <inline-formula><tex-math notation="LaTeX">$11.5\times$</tex-math></inline-formula> on the FPGA and <inline-formula><tex-math notation="LaTeX">$3\times$</tex-math></inline-formula> on the smartphone, as well as high efficiency: the FPGA processing time is <inline-formula><tex-math notation="LaTeX">$17\times$</tex-math></inline-formula> smaller than in a V100 GPU. To the best of our knowledge, we are the first to explore the possibility of compressing networks for radio frequency fingerprinting; as such, our experiments can be seen as a means of characterizing the informational capacity associated with this specific learning task.

Only Relative Speed Matters

Causal profiling is a novel and powerful profiling technique that quantifies the potential impact of optimizing a code segment on the program runtime. A key application of causal profiling is to analyze what-if scenarios which typically require a large number of experiments. Besides, the execution of a program highly depends on the underlying machine resources, e.g., CPU, network, storage, so profiling results on one device does not translate directly to another. This is a major bottleneck in our ability to perform scalable performance analysis and greatly limits cross-platform software development. In this paper, we address the above challenges by leveraging a unique property of causal profiling: only relative performance of different resources affects the result of causal profiling, not their absolute performance. We first analytically model and prove causal profiling, the missing piece in the seminal paper. Then, we assert the necessary condition to achieve virtual causal profiling on a secondary device. Building upon the theory, we design VCoz, a virtual causal profiler that enables profiling applications on target devices using measurements on the host device. We implement a prototype of VCoz by tuning multiple hardware components to preserve the relative execution speeds of code segments. Our experiments on benchmarks that stress different system resources demonstrate that VCoz can generate causal profiling reports of Nexus 6P (an ARM-based device) on a host MacBook (x86 architecture) with less than 16% variance.

Development of an integrated platform for hardware-in-the-loop evaluation of microgrids prior to site commissioning

This paper presents an integrated hardware-in-the-loop (HIL) platform for testing the operation and control of a real-world microgrid system prior to site commissioning. The proposed testing approach shows the value of setting up an integrated HIL platform to test multiple hardware devices (including the system-level controller, device controllers, and field devices). A test bed developed for the Borrego Springs community microgrid is used as an example to demonstrate the feasibility of the integrated platform. Comprehensive tests are carried out using the Borrego Springs test bed to validate the platform, meet the test objectives, and gain valuable insight prior to site commissioning. The selected test scenarios, initial conditions, events, test metrics, etc., are similar to those defined in IEEE P2030.8. The test objectives are to evaluate the microgrid controller and the operation of the microgrid. The HIL platform presented in this paper shows good value for microgrid testing in terms of its flexibility and scalability for testing various microgrids; its accuracy in its representation of the field; the comprehensiveness of the testing capability; and the efficiency of testing, which can reduce risks prior to field deployment.

CuRTAIL: ChaRacterizing and Thwarting AdversarIal Deep Learning

Recent advances in adversarial Deep Learning (DL) have opened up a new and largely unexplored surface for malicious attacks jeopardizing the integrity of autonomous DL systems. This article introduces CuRTAIL, a novel end-to-end computing framework to characterize and thwart potential adversarial attacks and significantly improve the reliability (safety) of a victim DL model. We formalize the goal of preventing adversarial attacks as an optimization problem to minimize the rarely observed regions in the latent feature space spanned by a DL network. To solve the aforementioned minimization problem, a set of complementary but disjoint modular redundancies are trained to validate the legitimacy of the input samples. The proposed countermeasure is unsupervised, meaning that no adversarial sample is leveraged to train modular redundancies. This, in turn, ensures the effectiveness of the defense in the face of generic attacks. We evaluate the robustness of our proposed methodology against the state-of-the-art adaptive attacks in a white-box setting considering that the adversary knows everything about the victim model and its defenders. Extensive evaluations for analyzing MNIST, CIFAR10, and ImageNet data corroborate the effectiveness of CuRTAIL framework against adversarial samples. The computations in each modular redundancy can be performed independently of the other redundancy modules. As such, CuRTAIL detection algorithm can be completely parallelized among multiple hardware settings to achieve maximum throughput. We further provide an open-source Application Programming Interface (API) to facilitate the adoption of the proposed framework for various applications.

Improving Facilitation of Student Communication Through Observational Feedback Within a Partner Instruction Model.

Purpose The purpose of this study was to further evaluate an eight-step partner instructional model developed by Kent-Walsh and McNaughton that has been demonstrated to improve implementation quality and fidelity among adults in clinical and educational settings who support the use of augmentative and alternative communication (AAC) for individuals with complex communication needs. Method This study examined the effectiveness of the eight-step model in a K-12 special education setting. Participants included 26 staff and 19 students. Effects on both communication partner modeling and student AAC system use were assessed. The study expanded upon prior research by employing a group design, including largely adolescent participants, and utilizing multiple AAC hardware and software types. Results Staff receiving training and coaching via the full eight-step model demonstrated gains in the percentage of utterances modeled, and their student partners increased mean length of utterance. The study failed to find statistically significant differences between the experimental group and a comparison group receiving only Stages 1-5 of the model. Conclusion Findings provide additional evidence for the viability of the eight-step instructional model as a methodology to promote the communication skills of students who utilize AAC, and also point to the advanced practice and feedback element of the model as a potential mediator of intervention outcomes.

Performance evaluation of the SM4 cipher based on field‐programmable gate array implementation

Information security is essential to ensure security of exchanged sensitive data in resource-constrained devices (RCDs) because they are used widely in the Internet of things (IoT). The implementation of special ciphers is required in these RCDs, as they have many limitations and constraints, such as low power/energy dissipation, and require low hardware resources. The SM4 cipher is one of the common block ciphers, which can be easily implemented and offers a high level of security. The objective of this study is to determine the optimum field-programmable gate array (FPGA) design for SM4 to facilitate reconfiguring the FPGA with an optimum design during operation. Various FPGA design options for SM4 ciphers are examined, and the performance metrics are modeled: power, energy, area, and speed. Scalar and pipelined designs with one or multiple hardware rounds are considered without altering the cipher algorithm. The results show that the best scalar implementation utilises less resources than the pipelined implementations by 7%. Alternatively, pipelined implementations perform better regarding speed and energy dissipation by 10 times and 40% of the scalar implementation, respectively. The pipeline implementations with eight or 16 rounds are optimum for continuous streams of data, and the two-round design is the optimum design across ciphers.

Architectural Supports for Block Ciphers in a RISC CPU Core by Instruction Overloading

We propose a novel computer architectural concept of instruction overloading to support block ciphers. Instead of adding new instructions, we extend only the execution of some existing instructions. The proposed method allows a central processing unit core to execute different operations for the same instructions, depending on the address of the data, similar to operator overloading in object-oriented languages. We first present an extension for the AES algorithm, then we demonstrate its enhanced applicability with two further extensions supporting multiple block ciphers and hardware masking. The first extension for AES is also applicable to add/AND-rotate-XOR-based block ciphers such as SIMON. The AES and SIMON encryption speed, on this extended core, is at least doubled and is significantly less affected by memory latency. In addition, the AES encryption code requires only 18% of the memory of the previous software implementation. The second extension can further support various block ciphers defined over GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> ), and the SM4 encryption speed is increased by at least 182%. The third extension provides correlation power analysis (CPA) resistance with a 66.6% area overhead but almost no speed overhead, whereas a typical software anti-CPA AES implementation requires at least hundreds of times the execution time.

An integrated platform for managing information in smart cities

This article focuses on defining the integrated platform for managing information in smart cities. We look into the smart city platforms that are increasingly used in today’s cities all around the world. Smart city platforms can be deployed on private, public or hybrid clouds, remote servers or onsite. By definition, a smart city platform integrates many different functional areas of the smart city in a single environment. The Smart city platform offers integrated functionality to coordinate intelligent city data, applications, solutions and services at one or more operational levels between multiple stakeholders with integrated functionality. By monitoring and analysing the use of urban assets, the government can distribute them to improve operational efficiency. The platform provides middleware and operational functionality across multiple software and hardware, integrates multiple communication protocols, and provides latent and free solutions for smart cities. Managing the huge amounts of data generated by IoT-based sensors and systems is a main challenge facing end users and providers. We show that smart city platforms serve to standardize data and information across many silo systems. It is demonstrated that they provide a common mechanism for visualizing and managing data to optimize the entire urban operation.

Model-Based Approach for Automatic Generation of Hardware Architectures for Robotics

Increasingly complex robotic platforms incorporate heterogeneous sensors and actuators. They are usually coupled with embedded computers but relying on software solutions not entirely suited for processing large amount of data concurrently and fast enough to keep real-time constrains. FPGAs are ideal candidates to enhance those systems computing capabilities while still being programmable. However, it is cumbersome to manually incorporate them into new or existing systems because providing accelerators with a specific integration capability limits their applicability. This work presents an approach to integrate multiple hardware accelerators into a robotic system. A model-based toolchain automatically generates the necessary hardware components (VHDL modules) from existing message specifications to exchange data with the accelerators. The goal is to seamlessly replace software components with FPGA-based ones while retaining the same communication interface. Instead of writing several hundred lines of VHDL, a dozen input specification lines are sufficient with our approach. The results are validated through an evaluation of all message specifications included in the latest Robot Operating System (ROS) versions. The 2295 messages evaluated show the robustness in our capabilities to support arbitrarily large ROS messages types, multiple data types, and nested messages. Moreover, our approach facilitates the extension from ROS1 to provide support for ROS2 easily. Finally, two use cases are shown to prove the feasibility of our approach on real applications. The first one incorporates a hardware accelerator for image processing obtained by High Level Synthesis (HLS) into an existing software architecture. The second one consists of a fully FPGA-based mobile platform with ROS features incorporated.

Evaluation of Portable Acceleration Solutions for LArTPC Simulation Using Wire-Cell Toolkit

The Liquid Argon Time Projection Chamber (LArTPC) technology plays an essential role in many current and future neutrino experiments. Accurate and fast simulation is critical to developing efficient analysis algorithms and precise physics model projections. The speed of simulation becomes more important as Deep Learning algorithms are getting more widely used in LArTPC analysis and their training requires a large simulated dataset. Heterogeneous computing is an efficient way to delegate computationally intensive tasks to specialized hardware. However, as the landscape of compute accelerators quickly evolves, it becomes increasingly difficult to manually adapt the code to the latest hardware or software environments. A solution which is portable to multiple hardware architectures without substantially compromising performance would thus be very beneficial, especially for long-term projects such as the LArTPC simulations. In search of a portable, scalable and maintainable software solution for LArTPC simulations, we have started to explore high-level portable programming frameworks that support several hardware backends. In this paper, we present our experience porting the LArTPC simulation code in the Wire-Cell Toolkit to NVIDIA GPUs, first with the CUDA programming model and then with a portable library called Kokkos. Preliminary performance results on NVIDIA V100 GPUs and multi-core CPUs are presented, followed by a discussion of the factors affiecting the performance and plans for future improvements.

IOT Energy Consumption Based on PSO-shortest Path Techniques

Background: The Internet of Thing is a network that enables multiple hardware devices, sensors and other home applications from electronically communicate with each other. New era such technology is increasing importance mainly due to the revolutionary development of information technologies. Methods: However, energy efficiency is still a big challenge facing IoT technology. Thus, it becomes an interesting topic for many researchers to investigate. Current work aims to reduce the energy consumption thereby introducing the shortest path technique and another new practicing for Particle Swarm Optimization algorithm in the Internet of Thing cooperative clusters. Results: The main concept is based on cluster heads cooperation with each other known as Cooperative Clusters to transfer information to the base station. The Primary results reveals a 17% and 16% reduction in energy consumption was achieved over the shortest path technique and Particle Swarm Optimization algorithm respectively. Results also show a remarkable improvement in the system lifetime due to the new applied scheme. Conclusion: The other method is by PSO algothrim at beginig it sending Randomly then it will select the path by using the feed back acknowledgment after that it will collect the information by sending it for the Cluster heads by updating the information status automatically. That’s why we discovered the PSO advantages than the others.

Biology-guided radiotherapy: redefining the role of radiotherapy in metastatic cancer.

The emerging biological understanding of metastatic cancer and proof-of-concept clinical trials suggest that debulking all gross disease holds great promise for improving patient outcomes. However, ablation of multiple targets with conventional external beam radiotherapy systems is burdensome, which limits investigation and utilization of complete metastatic ablation in the majority of patients with advanced disease. To overcome this logistical hurdle, technical innovation is necessary. Biology-guided radiotherapy (BgRT) is a new external beam radiotherapy delivery modality combining positron emission tomography-computed tomography (PET-CT) with a 6 MV linear accelerator. The key innovation is continuous response of the linear accelerator to outgoing tumor PET emissions with beamlets of radiotherapy at subsecond latency. This allows the deposited dose to track tumors in real time. Multiple new hardware and algorithmic advances further facilitate this low-latency feedback process. By transforming tumors into their own fiducials after intravenous injection of a radiotracer, BgRT has the potential to enable complete metastatic ablation in a manner efficient for a single patient and scalable to entire populations with metastatic disease. Future trends may further enhance the utility of BgRT in the clinic as this technology dovetails with other innovations in radiotherapy, including novel dose painting and fractionation schemes, radiomics, and new radiotracers.

Automatic Analysis Architecture of IoT Malware Samples

The weakness of the security measures implemented on IoT devices, added to the sensitivity of the data that they handle, has created an attractive environment for cybercriminals to carry out attacks. To do so, they develop malware to compromise devices and control them. The study of malware samples is a crucial task in order to gain information on how to protect these devices, but it is impossible to manually do this due to the immense number of existing samples. Moreover, in the IoT, coexist multiple hardware architectures, such as ARM, PowerPC, MIPS, Intel 8086, or x64-86, which enlarges even more the quantity of malicious software. In this article, a modular solution to automatically analyze IoT malware samples from these architectures is proposed. In addition, the proposal is subjected to evaluation, analyzing a testbed of 1500 malware samples, proving that it is an effective approach to rapidly examining malicious software compiled for any architecture.

Development of a low‐cost food color monitoring system

AbstractThe colorimetric analysis of food has gained much popularity in the last few decades. The present study reports the development of a low‐cost food color quality testing and process monitoring system. The proposed device consists of a hardware and a software (Color Magic) combination, which may allow the hardware to be used either for quality testing or process monitoring applications. In the quality‐testing mode, the software captures the image of the food products through the imaging system. Subsequently, the software processes the acquired image and computes color parameters in RGB (red, green, blue), CIELAB, and HSI (hue, saturation, intensity) color spaces. The software also synthesizes and displays the perceived color information in the display panel. The datalog of the sample color information can be sent to the user. Further, a separate software (Color Process), which is installed in a central server, was developed to implement a wireless star network topology for multi‐node process monitoring. The “Color Process” software allows users to acquire color information from multiple hardware. The software monitors the Hue from all the devices. It alerts the user via email if the Hue is beyond the range in any of the nodes. Finally, the device was tested for quality testing and process monitoring applications using colored placards and apple slices. The implementation of the wireless sensor network (WSN) in designing the multi‐node process monitoring makes the proposed device a unique system. This further would allow the device to be used for process monitoring at multiple remote locations.

Interactions between programmable shunt valves and magnetically controlled growing rods for scoliosis.

Although the advent of magnetic growing rod technology for scoliosis has provided a means to bypass multiple hardware lengthening operations, it is important to be aware that many of these same patients have a codiagnosis of hydrocephalus with magnet-sensitive programmable ventricular shunts. As the magnetic distraction of scoliosis rods has not previously been described to affect the shunt valve setting, the authors conducted an investigation to characterize the interaction between the two devices. In this ex vivo study, the authors carried out 360 encounters between four different shunt valve types at varying distances from the magnetic external remote control (ERC) used to distract the growing rods. Valve settings were examined before and after every interaction with the remote control to determine if there was a change in the setting. The Medtronic Strata and Codman Hakim valves were found to have setting changes at distances of 3 and 6 inches but not at 12 inches. The Aesculap proGAV and Codman Certas valves, typically described as MRI-resistant, did not have any setting changes due to the magnetic ERC regardless of distance. Although it is not necessary to check a shunt valve after every magnetic distraction of scoliosis growing rods, if there is concern that the magnetic ERC may have been within 12 inches (30 cm) of a programmable ventricular shunt valve, the valve should be checked at the bedside with a programmer or with a skull radiograph along with postdistraction scoliosis radiographs.

Intelligent Adaptation of Hardware Knobs for Improving Performance and Power Consumption

Current microprocessors include several knobs to modify the hardware behavior in order to improve performance, power, and energy under different workload demands. An impractical and time consuming offline profiling is needed to evaluate the design space to find the optimal knob configuration. Different knobs are typically configured in a decoupled manner to avoid the time-consuming offline profiling process. This can often lead to underperforming configurations and conflicting decisions that jeopardize system power-performance efficiency. Thus, a dynamic management of the different hardware knobs is necessary to find the knob configuration that maximizes system power-performance efficiency without the burden of offline profiling. In this article, we propose libPRISM, an infrastructure that enables the transparent management of multiple hardware knobs in order to adapt the system to the evolving demands of hardware resources in different workloads. libPRISM can minimize execution time, energy-delay product or power consumption by dynamically managing the SMT level, the data prefetcher, and the DVFS hardware knobs. Overall, the proposed solutions increase performance up to 130 percent (16.9 percent on average), reduce energy-delay product up to 80 percent, and reduce power consumption up to 33 percent depending on the target metric compared to the default knob configuration of the system.

Automated Bug Detection for High-level Synthesis of Multi-threaded Irregular Applications

Field Programmable Gate Arrays (FPGAs) are becoming an appealing technology in datacenters and High Performance Computing. High-Level Synthesis (HLS) of multi-threaded parallel programs is increasingly used to extract parallelism. Despite great leaps forward in HLS and related debugging methodologies, there is a lack of contributions in automated bug identification for HLS of multi-threaded programs. This work defines a methodology to automatically detect and isolate bugs in parallel circuits generated with HLS. The technique relies on hardware/software Discrepancy Analysis and exploits a pattern-matching algorithm based on Finite State Automata to compare multiple hardware and software threads. Overhead, advantages, and limitations are evaluated on designs generated with an open-source HLS compiler supporting OpenMP.

MULTITHREADED RENDERING FOR CROSS-PLATFORM 3D VISUALIZATION BASED ON VULKAN API

Abstract. The visualization of large-sized 3D geospatial models is a graphics intensive task. With ever increasing size and complexity, more computing resources are needed to attain speed and visual quality. Exploiting the parallelism and the multi-core performance of the Graphics Processing Unit (GPU), a cross-platform 3D viewer is developed based on the Vulkan API and modern C++. The proposed prototype aims at the visualization of a textured 3D mesh of the Cultural Heritage by enabling a multi-threaded rendering pipeline. The rendering workload is distributed across many CPU threads by recording multiple command buffers in parallel and coordinating the host and the GPU rendering phases. To ensure efficient multi-threading behavior and a minimum overhead, synchronization primitives are exploiting for ordering the execution of queues and command buffers. Furthermore, push-constants are used to send uniform data to the GPU and render passes to adapt to the tile-based rendering of the mobile devices. The proposed methodology and technical solution are designed, implemented and tested for Windows, MacOS and Android on Vulkan-compatible GPU hardware by compiling the same codebase. The benchmarking on multiple hardware, architectures and platforms explores the performance improvement for the different approaches compared to one-thread and showcase the potential of the 3D viewer to handle large datasets at no expense of visual quality and geometric fidelity in the absence of high-end technological resources.