Multiple-gate Field-effect Transistors Research Articles

Electrostatically formed nanowire (EFN) transistor—An ultrasensitive VOC and gas sensor

The perpetual need for high-performance volatile organic compound (VOC) sensors remains prevalent across diverse sectors including environmental health monitoring, industrial operations, and medical diagnostics. Within this context, the electrostatically formed nanowire (EFN) sensor, a silicon-on-insulator-based multiple-gate field-effect transistor, is an ultrasensitive and selective VOC and gas sensing platform. Unlike conventional silicon nanowires (also known for their superior sensitivity to chemical species), in EFN, the nanowire is defined electrostatically post-fabrication through appropriate biasing of the surrounding gates. The fabrication of the EFN leverages established CMOS compatible silicon processing technologies, facilitating the production of inexpensive, scalable, and robust sensors. By precisely controlling gate biases, a conductive channel with a tunable diameter is formed, allowing for the formation of nanowire with diameter below 20 nm. The adjustable size and shape of the nanowire offer tunable sensing parameters, including sensitivity, limit of detection, and dynamic range. The multiple parameters also yield a unique fingerprint for each VOC, thus enabling selective detection of VOCs. By simply altering the biasing configuration, a single EFN sensor can achieve high sensitivity and a broad dynamic range, which is limited in the case of physically defined silicon NW sensors. This review provides a comprehensive overview encompassing the EFN sensor's design, fabrication considerations, process flow, electrical characterization methods, sensing performances to VOCs, and gases at room temperature. Moreover, the scope of advanced sensor designs with array of EFN sensors and integrated heaters is also discussed. Finally, some future perspectives of this technology are presented.

Technology and Modeling of Nonclassical Transistor Devices

This paper presents a comprehensive outlook for the current technology status and the prospective upcoming advancements. VLSI scaling trends and technology advancements in the context of sub-10-nm technologies are reviewed as well as the associated device modeling approaches and compact models of transistor structures are considered. As technology goes into the nanometer regime, semiconductor devices are confronting numerous short-channel effects. Bulk CMOS technology is developing and innovating to overcome these constraints by introduction of (i) new technologies and new materials and (ii) new transistor architectures. Technology boosters such as high-k/metal-gate technologies, ultra-thin-body SOI, Ge-on-insulator (GOI), AIII–BV semiconductors, and band-engineered transistor (SiGe or Strained Si-channel) with high-carrier-mobility channels are examined. Nonclassical device structures such as novel multiple-gate transistor structures including multiple-gate field-effect transistors, FD-SOI MOSFETs, CNTFETs, and SETs are examined as possible successors of conventional CMOS devices and FinFETs. Special attention is devoted to gate-all-around FETs and, respectively, nanowire and nanosheet FETs as forthcoming mainstream replacements of FinFET. In view of that, compact modeling of bulk CMOS transistors and multiple-gate transistors are considered as well as BSIM and PSP multiple-gate models, FD-SOI MOSFETs, CNTFET, and SET modeling are reviewed.

Universal core model for multiple-gate field-effect transistors with short channel and quantum mechanical effects

A universal core model for multiple-gate (MG) field-effect transistors (FETs) with short channel effects (SCEs) and quantum mechanical effects (QMEs) is proposed. By using a Young’s approximation based solution for one-dimensional Poisson’s equations the total inversion charge density (Qinv) in the channel is modeled for double-gate (DG) and surrounding-gate SG (SG) FETs, following which a universal charge model is derived based on the similarity of the solutions, including for quadruple-gate (QG) FETs. For triple-gate (TG) FETs, the average of DG and QG FETs are used. A SCEs model is also proposed considering the potential difference between the channel’s surface and center. Finally, a QMEs model for MG FETs is developed using the quantum correction compact model. The proposed universal core model is validated on commercially available three-dimensional ATLAS numerical simulations.

The Electrostatically Formed Nanowire: A Novel Platform for Gas-Sensing Applications.

The electrostatically formed nanowire (EFN) gas sensor is based on a multiple-gate field-effect transistor with a conducting nanowire, which is not defined physically; rather, the nanowire is defined electrostatically post-fabrication, by using appropriate biasing of the different surrounding gates. The EFN is fabricated by using standard silicon processing technologies with relaxed design rules and, thereby, supports the realization of a low-cost and robust gas sensor, suitable for mass production. Although the smallest lithographic definition is higher than half a micrometer, appropriate tuning of the biasing of the gates concludes a conducting channel with a tunable diameter, which can transform the conducting channel into a nanowire with a diameter smaller than 20 nm. The tunable size and shape of the nanowire elicits tunable sensing parameters, such as sensitivity, limit of detection, and dynamic range, such that a single EFN gas sensor can perform with high sensitivity and a broad dynamic range by merely changing the biasing configuration. The current work reviews the design of the EFN gas sensor, its fabrication considerations and process flow, means of electrical characterization, and preliminary sensing performance at room temperature, underlying the unique and advantageous tunable capability of the device.

Total Ionizing Dose Response of Multiple-Gate Nanowire Field Effect Transistors

This paper investigates the total ionizing dose (TID) response of nanoscaled field-effect transistors (FET) made of silicon multiple-gate nanowire (NW). The NWFET architecture relies on its remarkable electrostatic properties to push “silicon”-based technologies much deeper into device scaling than present FinFETs. However, as commonly observed when a new device or technology concept is proposed, such as shallow trench isolation and silicon-on-insulator or FinFET, TID effects reveal unexpected behaviors that can permanently modify pristine device electrical characteristics. This is why this paper discusses the impact of several parameters including the NWFET design and the transistor’s type to get thorough insights into the NWFET TID behavior.

Electrostatic Limit of Detection of Nanowire-Based Sensors.

Scanning gate microscopy is used to determine the electrostatic limit of detection (LOD) of a nanowire (NW) based chemical sensor with a precision of sub-elementary charge. The presented method is validated with an electrostatically formed NW whose active area and shape are tunable by biasing a multiple gate field-effect transistor (FET). By using the tip of an atomic force microscope (AFM) as a local top gate, the field effect of adsorbed molecules is emulated. The tip induced charge is quantified with an analytical electrostatic model and it is shown that the NW sensor is sensitive to about an elementary charge and that the measurements with the AFM tip are in agreement with sensing of ethanol vapor. This method is applicable to any FET-based chemical and biological sensor, provides a means to predict the absolute sensor performance limit, and suggests a standardized way to compare LODs and sensitivities of various sensors.

Template-assisted selective epitaxy of III–V nanoscale devices for co-planar heterogeneous integration with Si

III–V nanoscale devices were monolithically integrated on silicon-on-insulator (SOI) substrates by template-assisted selective epitaxy (TASE) using metal organic chemical vapor deposition. Single crystal III–V (InAs, InGaAs, GaAs) nanostructures, such as nanowires, nanostructures containing constrictions, and cross junctions, as well as 3D stacked nanowires were directly obtained by epitaxial filling of lithographically defined oxide templates. The benefit of TASE is exemplified by the straightforward fabrication of nanoscale Hall structures as well as multiple gate field effect transistors (MuG-FETs) grown co-planar to the SOI layer. Hall measurements on InAs nanowire cross junctions revealed an electron mobility of 5400 cm2/V s, while the alongside fabricated InAs MuG-FETs with ten 55 nm wide, 23 nm thick, and 390 nm long channels exhibit an on current of 660 μA/μm and a peak transconductance of 1.0 mS/μm at VDS = 0.5 V. These results demonstrate TASE as a promising fabrication approach for heterogeneous material integration on Si.

Proton Radiation Effects on the Analog Performance of Bulk n- and p-FinFETs

The Multiple Gate Field Effect Transistor (MuGFET) is one of the technologies that can follow Moore’s law for 22nm and 14nm technologies [1]. The MuGFET must be narrow to obtain a better electrostatic coupling, consequently, a better transistor performance. Besides that, the vertical triple-gate devices (3D-transistors) can be fabricated either on silicon or on Silicon-On-Insulator (SOI) substrates [2].This paper evaluates the impact of 60MeV Proton radiation on triple gate Bulk FinFETs, for both n and p types, comparing them with their respective non radiated devices. Not only the analog parameters, such as: intrinsic voltage gain (AV) have been evaluated, but also the threshold voltage (VT) and the gate induced drain leakage (GIDL) current.The devices used in this work have been fabricated on a p-type silicon substrate, in Imec/Belgium. The device dimensions are fin height (HFin) of 40 nm; fin width (WFin) of 20 nm, 130 nm and 1µm; channel length (L) of 35 nm, 70 nm and 1µm and a gate stack composed by 1 nm (SiO2), 2.1 nm (HfSiO), metal gate of 5 nm (TiN). Besides that, all the triple gate structures have 5 fins in parallel and the wafer doping concentration is around 1x1015 cm-3. The devices were submitted to a 60MeV proton irradiation and fluence of 10¹² cm-2, which has been performed at the cyclotron facility in Louvain-la-Neuve (Belgium). First of all, the drain current as a function of gate voltage is analyzed for Bulk FinFETs with both p and n type transistors, figure 1. Although the narrow devices are usually insensitive to a radiation environment, in this work the narrowest nFinFET device (WFin = 20 nm) presents a high level of leakage current in the subthreshold region after the radiation, which is opposite to the SOI FinFET technology [3]. This unexpected behavior is related to a parasitic conduction, which occurs at the silicon/STI (shallow trench isolation) interface and bulk silicon region due to the increase of oxide charges and consequently the threshold voltage reduction after proton radiation. For the wide fin nFinFETs, the anti-punch-through implantation is more effective than in the narrow ones, resulting in a barrier that reduces the leakage current from the parasitic transistor. On the other hand, for pFinFETs the radiation effect is apparently independent of the fin dimensions, since the VT of the parasitic transistor is more negative than the main one. Therefore, the main transistor turns on the device before the parasitic one and as a result, no degradation in IDS was observed.For narrow nFinFETs, the subthreshold swing (SS) will be degraded and dominated by the parasitic channel. On the other hand, the subthreshold slope for pFinFETs was not affected by radiation.The pFinFETs present no significant variation in the VT, it was observed as a function of L and WFin (figure2), neither in the pre, nor in the post radiated devices. On the other hand, the nFinFETs show a slight reduction of VT values after irradiation. It is due to the positive charge trapped in the shallow trench isolation (STI), consequently, the VT decreases (~ 50 mV).The gate induced drain leakage current (ID_GIDL) can be seen in Figure 3. It is possible to observe that the nFinFET is strongly affected by the irradiation for narrow fins, which presents a large radiation-induced increase of ID_GIDL due to the predominance of the parasitic conduction in this region, as discussed previously. On the other hand, for pFinFET there is almost no radiation effect for different fin width dimensions.The main basic analog parameters were analyzed in figure 4 showing that the intrinsic voltage gain (AV) reduces as the L decreases, it is related to the lateral electrical field penetration into the channel region. Similar as for the other analyzed parameters, the radiation effects are more pronounced in the nFinFETs than the pFinFETs also for the AV. [1] ITRS 2013 [Online]. Available: http://public.itrs.net/Links/2013ITRS/2013Chapters/2013PIDS_Summary.pdf[2] T. Chiarella et al., Solid-State Electronics, vol. 54, pp. 855–860, May 2010. [3] P.G.D. Agopian et al., IEEE Transactions on Nuclear Science, Vol. 59, No. 4, pp. 707–713 August 2012. Figure 1

${\rm In}_{0.53}{\rm Ga}_{0.47}{\rm As}$ Multiple-Gate Field-Effect Transistors With Selectively Regrown Channels

We report on In0.53Ga0.47As n-channel multiple-gate field-effect transistors (MuGFETs or FinFETs) with a novel method of selectively regrown lateral (parallel to substrate) nanowires as channels. The device exhibits a minimum subthreshold slope of 85 mV/decade and drain-induced barrier lowering of 88 mV/V at VDS=0.05 V and LG=200 nm. At VDS=0.5 V, gm,max=1.67 mS/μm is achieved (LG=32 nm). The extrapolated cutoff frequency fT of 210 GHz and the maximum oscillation frequency fmax of 250 GHz are the highest of any reported III-V multiple-gate MOSFET.

MULTIPLE GATE FIELD-EFFECT TRANSISTORS FOR FUTURE CMOS TECHNOLOGIES

This is a review paper on the topic of multiple gate field effect transistors: MuGFETs, or FinFETs, as they are called. First, the motivation behind multiple gate FETs is presented. This is followed by looking at the evolution of FinFET technologies; the main flavors (variants) of Multigate FETs; and their advantages/disadvantages. The physics and technology of these devices is briefly discussed. Results are then presented which show the performance figures of merit of FinFETs, and their strengths and weaknesses. Finally, a perspective on the future of the FinFET technology is presented.

Gate Stack Reliability of MOSFETs With High-Mobility Channel Materials: Bias Temperature Instability

To sustain the historical trend of performance enhancement of metal-oxide-semiconductor field-effect transistors (MOSFETs) for high-performance and low-power logic applications beyond the 10-nm technology node, InGaAs and Ge or GeSn are promising alternative channel materials to replace strained Si due to their high electron and hole mobility values, respectively. In addition to delivering higher drive current at a reduced supply voltage VDD, another challenge in integrating these materials is to achieve device lifetimes equal or better than that of the Si counterpart. In this paper, we report the results of bias temperature instability (BTI) investigations on InGaAs n-channel MOSFETs (nMOSFETs) and GeSn p-channel MOSFETs (pMOSFETs) with a common surface passivation and gate stack formation technology. While GeSn planar pMOSFETs with Si passivation show excellent negative bias temperature instability (NBTI) reliability, positive bias temperature instability (PBTI) reliability of InGaAs nMOSFETs needs further improvement. The strain effect on NBTI of Ge pMOSFETs will be discussed. The NBTI of Ge multiple-gate field-effect transistors (MuGFETs) will be also reported. In addition, we review the status of the BTI reliability for MOSFETs with high-mobility channel materials and discuss issues of BTI characterization of transistors with small bandgap channel materials and the importance of interface quality between channel materials and gate dielectrics for device BTI performance.

Post-CMOS FinFET Integration of Bismuth Telluride and Antimony Telluride Thin-Film-Based Thermoelectric Devices on SoI Substrate

This letter reports, for the first time, heterogeneous integration of bismuth telluride (Bi2Te3) and antimony telluride (Sb2Te3) thin-film-based thermoelectric (TE) devices on a CMOS substrate. The TE films are deposited on a silicon-on-insulator substrate with FinFETs (3-D multiple gate field effect transistors) via a characterized TE-film coevaporation and shadow-mask patterning process using predeposition surface treatment methods for reduced TE-metal contact resistance. As a demonstration vehicle, a 2 × 2 mm2-sized integrated planar thermoelectric generator (TEG) is shown to harvest 0.7 μW from 21-K temperature gradient. Transistor performance showed no significant change upon post-CMOS TEG integration, indicating, for the first time, the CMOS compatibility of the Bi2Te3 and Sb2Te3 thin films, which could be leveraged for realization of high-performance integrated micro-TE harvesters and coolers.

Germanium Multiple-Gate Field-Effect Transistor With In Situ Boron-Doped Raised Source/Drain

We report the first demonstration of a p-channel Ω-gate Germanium (Ge) multiple-gate field-effect transistor (MuGFET) on a Germanium-on-Insulator (GeOI) substrate with in situ Boron (B)-doped Ge (Ge:B) raised source/drain (RSD). Detailed process optimization on epitaxial growth of Ge on patterned GeOI samples is discussed. Process integration of Ge:B RSD into Ge MuGFETs using a CMOS compatible process flow is documented. Electrical characteristics of Ge MuGFETs with RSD are reported.

Germanium Multiple-Gate Field-Effect Transistors Formed on Germanium-on-Insulator Substrate

We demonstrate the integration of high performance p-channel Germanium Multiple-Gate Field-Effect Transistors (MuGFETs) on a Germanium-on-Insulator substrate. Detailed process conditions are documented in this paper. The effects of Ge fin doping concentration on the electrical performance of Ge MuGFETs are discussed, and this could be useful for further device optimization. It is found that a higher fin doping leads to better control of short-channel efforts of Ge MuGFETs but degrades the on-state current and transconductance. High on-state current for Ge MuGFETs is reported in this paper.

A Universal Core Model for Multiple-Gate Field-Effect Transistors. Part II: Drain Current Model

A universal drain current model for multiple-gate field-effect transistors (FETs) (Mug-FETs) is proposed. In Part I, a universal charge model was derived using the arbitrary potential method. Using this charge model, Pao-Sah's integral is analytically carried out by approximating its integrand. The model describes both the subthreshold inversion for undoped FETs and the effects of finite doping density in the channel. With an explicit and continuous expression, the proposed drain current model covers all regions of device operation: subthreshold, linear, and saturation. The accuracy from the proposed model is comparable with that from well-known previous models for double-gate (DG) and cylindrical gate-all-around (Cy-GAA) FETs with an undoped channel. In addition, the model shows good agreement with 2-D and 3-D numerical simulations for doped-channel multiple-gate structures such as single-gate, DG, triple-gate, rectangular gate-all-around, and Cy-GAA FETs. The proposed model is well suited to be a core model for Mug-FETs due to its good computational efficiency and high accuracy; hence, it is useful for compact modeling.

A Universal Core Model for Multiple-Gate Field-Effect Transistors. Part I: Charge Model

A universal core model for multiple-gate field-effect transistors (Mug-FETs) is proposed. The proposed charge and drain current models are presented in Parts I and II, respectively. It is first demonstrated that an exact potential profile in the entire channel is not necessary for the derivation of accurate charge models in inversion-mode FETs. With application of this new concept, a universal charge model is derived for Mug-FETs by assuming an arbitrary channel potential profile, which simplifies the mathematical formulation. Thereafter, using the Pao-Sah integral, a drain current model is obtained from the charge model of Part I. The proposed model can be expressed as an explicit and continuous form for all operation regimes; therefore, it is well suited for compact modeling to support fast circuit simulations. The model shows good agreement with 2-D and 3-D numerical simulations for several multiple-gate structures, such as single-gate, double-gate, triple-gate, rectangular gate-all-around, and cylindrical gate-all-around FETs.

Accurate Prediction of Thermal Resistance of FET by Detailed Modeling of Heat Generation and Backend Stackup

In typical thermal modeling of a FET (field effect transistor) structure, the power could be modeled as the heat generation, which is averaged under the entire gate length (gate averaged). However, it is found from the electrical potential field within the channel that the heat generation is actually distributed all the way from source to drain with a heavy concentration around the gate edge at the drain side. In a typical case, the peak of the heat distribution is almost four times of the gate averaged. Therefore, accurate modeling of the heat generation averaging over a much smaller region near the gate edge (edge averaged) makes a significant difference. This paper focuses on the comparison of the edge averaged versus the gate averaged modeling development. Furthermore, the detailed topology of the backend stackup layers and their relative impacts on heat dissipation paths are evaluated and the practical simplification is proposed in the modeling development. The result shows that, for a single gate FET die, the thermal resistance is found to be 26% more than that of the gate averaged approach. For a multiple gate FET die, both methods give the same surface temperature on the top surface layer. However, the temperature difference (ΔTjs) between the junction and the top surface is different between the two heat averaging approaches and the edge averaged approach prediction doubles that of the gate averaged approach. It is also found that ΔTjs is independent of number of gates and only depends on the backend stackup details between source and drain.

Low-Frequency Noise Study of p-Channel Bulk MuGFETs

The low-frequency (LF) noise in p-channel bulk Multiple-Gate Field-Effect Transistors (MuGFETs) with 2.5 nm SiON gate oxide has been investigated in the ohmic regime from weak to strong inversion. It is shown that both 1/f-like noise and Generation-Recombination (GR) noise are present, giving rise to a wide device-to-device scatter in the spectral density. The 1/f noise is dominated by number fluctuations from which an effective trap density in the range 5×1017 cm-3eV-1 has been derived. At the same time, it is demonstrated that the GR noise originates from traps in the gate oxide.

Drive current enhancement in p-tunnel FETs by optimization of the process conditions

We show the impact of process parameters on the electrical performance of complementary Multiple-Gate Tunnel Field Effect Transistors (MuGTFETs), implemented in a Multiple-Gate Field Effect Transistors (MuGFETs) technology compatible with standard CMOS processing. Firstly, we assess the impact of the gate oxide thickness on the tunneling performance. Secondly, we investigate the effect of the doping concentration and profile by implementing different doping conditions. Thirdly, three different annealing conditions are compared: spike anneal, sub-ms laser anneal and low temperature anneal for Solid Phase Epitaxy Regrowth (SPER). In case of SPER anneal a record drive current of 46μA/μm at VDD of −1.2V and IOFF of 5pA/μm for Si pTFETs is reported. The enhanced current is given by the position of the silicide at the n+side close to the gate. Silicide engineering opens a new opportunity to optimize tunnel devices.

Modeling of Ionizing Radiation-Induced Degradation in Multiple Gate Field Effect Transistors

The radiation response of advanced non-planar multiple gate field effect transistors (MuGFETs) has been shown to have a strong dependence on fin width (W). The incorporation of total ionizing dose (TID) effects into a physics-based surface-potential compact model allows for the effects of radiation-induced degradation in MuGFET devices to be modeled in circuit simulators, e.g., SPICE. A set of extracted parameters are used in conjunction with closed-form expressions for the surface potential, thereby enabling accurate modeling of the radiation-response and its dependence on W . Total ionizing dose (TID) experiments and two-dimensional (2D) TCAD simulations are used to validate the compact modeling approach presented in this paper.