Proton Radiation Effects on the Analog Performance of Bulk n- and p-FinFETs

Abstract

The Multiple Gate Field Effect Transistor (MuGFET) is one of the technologies that can follow Moore’s law for 22nm and 14nm technologies [1]. The MuGFET must be narrow to obtain a better electrostatic coupling, consequently, a better transistor performance. Besides that, the vertical triple-gate devices (3D-transistors) can be fabricated either on silicon or on Silicon-On-Insulator (SOI) substrates [2].This paper evaluates the impact of 60MeV Proton radiation on triple gate Bulk FinFETs, for both n and p types, comparing them with their respective non radiated devices. Not only the analog parameters, such as: intrinsic voltage gain (AV) have been evaluated, but also the threshold voltage (VT) and the gate induced drain leakage (GIDL) current.The devices used in this work have been fabricated on a p-type silicon substrate, in Imec/Belgium. The device dimensions are fin height (HFin) of 40 nm; fin width (WFin) of 20 nm, 130 nm and 1µm; channel length (L) of 35 nm, 70 nm and 1µm and a gate stack composed by 1 nm (SiO2), 2.1 nm (HfSiO), metal gate of 5 nm (TiN). Besides that, all the triple gate structures have 5 fins in parallel and the wafer doping concentration is around 1x1015 cm-3. The devices were submitted to a 60MeV proton irradiation and fluence of 10¹² cm-2, which has been performed at the cyclotron facility in Louvain-la-Neuve (Belgium). First of all, the drain current as a function of gate voltage is analyzed for Bulk FinFETs with both p and n type transistors, figure 1. Although the narrow devices are usually insensitive to a radiation environment, in this work the narrowest nFinFET device (WFin = 20 nm) presents a high level of leakage current in the subthreshold region after the radiation, which is opposite to the SOI FinFET technology [3]. This unexpected behavior is related to a parasitic conduction, which occurs at the silicon/STI (shallow trench isolation) interface and bulk silicon region due to the increase of oxide charges and consequently the threshold voltage reduction after proton radiation. For the wide fin nFinFETs, the anti-punch-through implantation is more effective than in the narrow ones, resulting in a barrier that reduces the leakage current from the parasitic transistor. On the other hand, for pFinFETs the radiation effect is apparently independent of the fin dimensions, since the VT of the parasitic transistor is more negative than the main one. Therefore, the main transistor turns on the device before the parasitic one and as a result, no degradation in IDS was observed.For narrow nFinFETs, the subthreshold swing (SS) will be degraded and dominated by the parasitic channel. On the other hand, the subthreshold slope for pFinFETs was not affected by radiation.The pFinFETs present no significant variation in the VT, it was observed as a function of L and WFin (figure2), neither in the pre, nor in the post radiated devices. On the other hand, the nFinFETs show a slight reduction of VT values after irradiation. It is due to the positive charge trapped in the shallow trench isolation (STI), consequently, the VT decreases (~ 50 mV).The gate induced drain leakage current (ID_GIDL) can be seen in Figure 3. It is possible to observe that the nFinFET is strongly affected by the irradiation for narrow fins, which presents a large radiation-induced increase of ID_GIDL due to the predominance of the parasitic conduction in this region, as discussed previously. On the other hand, for pFinFET there is almost no radiation effect for different fin width dimensions.The main basic analog parameters were analyzed in figure 4 showing that the intrinsic voltage gain (AV) reduces as the L decreases, it is related to the lateral electrical field penetration into the channel region. Similar as for the other analyzed parameters, the radiation effects are more pronounced in the nFinFETs than the pFinFETs also for the AV. [1] ITRS 2013 [Online]. Available: http://public.itrs.net/Links/2013ITRS/2013Chapters/2013PIDS_Summary.pdf[2] T. Chiarella et al., Solid-State Electronics, vol. 54, pp. 855–860, May 2010. [3] P.G.D. Agopian et al., IEEE Transactions on Nuclear Science, Vol. 59, No. 4, pp. 707–713 August 2012. Figure 1