Multiple-control Toffoli Research Articles

An Algorithm for Reversible Logic Circuit Synthesis Based on Tensor Decomposition

An algorithm for reversible logic synthesis is proposed. The task is, for a given n -bit substitution map, to find a sequence of reversible logic gates that implements the map. The gate library adopted in this work consists of multiple-controlled Toffoli gates with m control bits, where m ∈ {0, …, n − 1}. Controlled gates with large m (> 2) are then further decomposed into smaller gates ( m ≤ 2). A primary goal in designing the algorithm is to reduce the number of Toffoli gates which is known to be universal. The main idea is to view an n -bit substitution map as a rank-2 n tensor, and to transform it such that the resulting map can be written as a tensor product of a rank-(2 n − 2) tensor and the 2 × 2 identity matrix. It can then be seen that the transformed map acts nontrivially on n − 1 bits only, meaning that the map to be synthesized becomes ( n − 1)-bit substitution. This size reduction process is iteratively applied until it reaches a tensor product of only 2 × 2 matrices. The time complexity of the algorithm is exponential in n as most previously known heuristic algorithms for reversible logic synthesis are, but it terminates within reasonable time for not too large n which may find practical uses. As stated earlier, our primary target is to reduce the number of Toffoli gates in the output circuit. Benchmark results show that the algorithm works well for hard benchmark functions, but it does not seem advantageous when the function is structured. As an application, the algorithm is applied to find reversible circuits for cryptographic substitution boxes, which are often required in quantum cryptanalysis.

A Multiple Controlled Toffoli Driven Adaptive Quantum Neural Network Model for Dynamic Workload Prediction in Cloud Environments.

The key challenges in cloud computing encompass dynamic resource scaling, load balancing, and power consumption. Accurate workload prediction is identified as a crucial strategy to address these challenges. Despite numerous methods proposed to tackle this issue, existing approaches fall short of capturing the high-variance nature of volatile and dynamic cloud workloads. Consequently, this paper introduces a novel model aimed at addressing this limitation. This paper presents a novel Multiple Controlled Toffoli-driven Adaptive Quantum Neural Network (MCT-AQNN) model to establish an empirical solution to complex, elastic as well as challenging workload prediction problems by optimizing the exploration, adaption, and exploitation proficiencies through quantum learning. The computational adaptability of quantum computing is ingrained with machine learning algorithms to derive more precise correlations from dynamic and complex workloads. The furnished input data point and hatched neural weights are refitted in the form of qubits while the controlling effects of Multiple Controlled Toffoli (MCT) gates are operated at the hidden and output layers of Quantum Neural Network (QNN) for enhancing learning capabilities. Complimentarily, a Uniformly Adaptive Quantum Machine Learning (UAQL) algorithm has evolved to functionally and effectually train the QNN. The extensive experiments are conducted and the comparisons are performed with state-of-the-art methods using four real-world benchmark datasets. Experimental results evince that MCT-AQNN has up to 32%-96% higher accuracy than the existing approaches.

A new design of parity-preserving reversible multipliers based on multiple-control toffoli synthesis targeting emerging quantum circuits

A new design of parity-preserving reversible multipliers based on multiple-control toffoli synthesis targeting emerging quantum circuits

MPMCT gate decomposition method reducing T-depth quickly in proportion to the number of work qubits

We propose a method for efficient mixed polarity multiple controlled Toffoli (MPMCT) gate decomposition from the perspective of a cost metric related to Toffoli gates, namely Toffoli-depth. When using the technique presented in a previous study, there is a range in which Toffoli-depth (consequently T-depth) of the implemented circuit increases proportionally as the number of provided (clean) work qubits increases. In other words, using the previous technique may result in more inefficient MPMCT gates even though the number of helpful work qubits has increased. In this work, a technique is devised to provide sufficient help from clean work qubits at the central part of the implemented circuit as many as possible, thereby addressing the issues with the previous technique. Meanwhile, one of the representative algorithms that use MPMCT gates is Grover’s algorithm. We show the implementation results for MPMCT gates according to the number of work qubits, using Grover’s algorithm as an example. It is experimentally demonstrated that T-depth decreases much more quickly when using our method than the previous method.

Multiple-Controlled Toffoli and Multiple-Controlled Fredkin Reversible Logic Gates-Based Reversible Synchronous Counter Design

The counters that change their transition using a clock signal are called synchronous counters. While designing a synchronous counter circuit, the power consumption and the delay are the major issues. Several synchronous counters were designed previously with the help of flip flops, but they did not provide good results. The existing synchronous counters increased power consumption and delay and decreased the speed. To overcome these issues, in this manuscript, a reversible synchronous counter is designed utilizing Multiple-Controlled Toffoli (MCT) and Multiple-Controlled Fredkin (MCF) reversible logic gates. Here, three JK flip-flop designs, such as JK1, JK2, and JK3 are designed for a reversible synchronous counter. Then JK1 and JK2 are structured by MCT. Whereas the JK3 flip-flop design is designed under MCF reversible logic gates. Coding is carried out Verilog, and then the proposed Reversible synchronous counter design (RSCD) is synthesized and implemented on FPGA using a Xilinx ISE 14.5 System generator. Here, performance metrics, such as delay, power, maximum counting rate, and total equivalent gate counts are examined. The efficiency of the proposed RSCD-MCT-MCF design attains gate counts of 23.45%, 28.94%, and 29.04% and is compared to the existing designs, such as Effective Designing of Reversible Synchronous Counters in Nanoscale (SCD-MTG), effective designing for reversible sequential circuits (SCD-3TG-4FG), designing of synchronous decimal counter utilizing reversible Toffoli–FredkinNetlist (SCD-TOF2).

Baugh-Wooley Multiplier design using Multiple Control Toffoli and Multiple Control Fredkin reversible logic gates

AbstractMost error-resilient media processing applications use multipliers as their basic building blocks. These are power-consumption and computationally intensive modules. In the existing works, several types of the multipliers were used to improve the hardware capacity, but those methods did not provide sufficient results. Therefore, in this manuscript, a Baugh-Wooley Multiplier design using Multiple Control Toffoli (MCT) and Multiple Control Fredrick gate (MCF) Reversible Logic gate (BWM-MCT-MCF) will be analyzed. Initially, Reversible Full Adder (RFA) is designed using Multiple Control Toffoli and Multiple Control Fredrick gate Reversible Logic gates. Then the proposed Reversible Full Adder is used in Baugh-Wooley Multiplier. By this, it reduces the hardware complexity with higher speed, lower area, lower power consumption. The proposed BWM-MCT-MCF multiplier is implemented in MATLAB, its performance shows lower Garbage output 22.78%, 24.88%, 20.95% compared with the existing designs, like BWM-FG-FRG, BWM-RL-TG, BWM-TG-FG respectively. Then the designed BWM-MCT-MCF is implemented using Xilinx ISE tool with the Virtex 5 device. From this, the performance of the proposed FPGA-BWM-MCT-MCF method shows lower delay 23.77%, 16.86% compared with the existing designs, like FPGA-BWM-RL-TG, FPGA-BWM-TG-FG respectively.

A novel design of reversible quantum multiplier based on multiple-control toffoli synthesis

A novel design of reversible quantum multiplier based on multiple-control toffoli synthesis

An Efficient Method to Decompose and Map MPMCT Gates That Accounts for Qubit Placement

Mixed-Polarity Multiple-Control Toffoli (MPMCT) gates are generally used to implement large control logic functions for quantum computation. A logic circuit consisting of MPMCT gates needs to be mapped to a quantum computing device that invariably has a physical limitation, which means we need to (1) decompose the MPMCT gates into one- or two-qubit gates, and then (2) insert SWAP gates so that all the gates can be performed on Nearest Neighbor Architectures (NNAs). Up to date, the above two processes have only been studied independently. In this work, we investigate that the total number of gates in a circuit can be decreased if the above two processes are considered simultaneously as a single step. We developed a method that inserts SWAP gates while decomposing MPMCT gates unlike most of the existing methods. Also, we consider the effect on the latter part of a circuit carefully by considering the qubit placement when decomposing an MPMCT gate. Experimental results demonstrate the effectiveness of our method.

Template-based mapping of reversible circuits to IBM quantum computers

In order to make the most of the increasing computational power of recently developed quantum computers, it is crucial to perform an efficient mapping of a given quantum circuit that realizes the desired quantum algorithm to the targeted quantum computer (so-called technology mapping). In most cases, the limitations of the targeted quantum hardware have not been taken into account when generating these quantum circuits in the first place. Thus, the technology mapping is likely to induce a considerable overhead for such circuits in order prepare them for the execution on the actual device. In this work, we consider the realization of reversible circuits consisting of multiple-controlled Toffoli gates on IBM quantum computers. Using templates for the realization of the reversible/quantum gates allows to perform a topology-aware decomposition of MCT gates that exhibits the potential of significant reductions of the technology mapping overhead.

The Optimization and Application of 3-Bit Hermitian Gates and Multiple Control Toffoli Gates

The well-known 3-bit Hermitian gate (a Toffoli gate) has been implemented using Clifford + T circuits. Compared with the Peres gate, its implementation circuit requires more controlled-NOT (CNOT) gates. However, the Peres gate is not Hermitian. This paper reports four 3-bit Hermitian gates named LI gates. Whose realized circuits have the same T-count, T-depth, and CNOT-count as the Peres gate. Furthermore, two decomposition methods of a multiple control Toffoli (MCT) gate are proposed for different primary optimization goals. Then, we design the equality, less-than, and full comparators with the minimum circuit width using proposed Hermitian gates and optimized MCT gates. A fault-tolerant circuit is required for robust quantum computing. Clifford+T circuits are accepted solutions for fault-tolerant implementation. Considering T-count, T-depth, CNOT-count, and circuit width as the primary optimization goals, we design the optimized Clifford + T circuits of three comparators using LI gates and optimized MCT gates. Comparison and analysis show that the proposed comparators have better overall performances for T-count, T-depth, CNOT-count, and circuit width than the best-known comparators without quantum measurements.

A multi-commodity network model for optimal quantum reversible circuit synthesis.

Quantum computing is a newly emerging computing environment that has recently attracted intense research interest in improving the output fidelity, fully utilizing its high computing power from both hardware and software perspectives. In particular, several attempts have been made to reduce the errors in quantum computing algorithms through the efficient synthesis of quantum circuits. In this study, we present an application of an optimization model for synthesizing quantum circuits with minimum implementation costs to lower the error rates by forming a simpler circuit. Our model has a unique structure that combines the arc-subset selection problem with a conventional multi-commodity network flow model. The model targets the circuit synthesis with multiple control Toffoli gates to implement Boolean reversible functions that are often used as a key component in many quantum algorithms. Compared to previous studies, the proposed model has a unifying yet straightforward structure for exploiting the operational characteristics of quantum gates. Our computational experiment shows the potential of the proposed model, obtaining quantum circuits with significantly lower quantum costs compared to prior studies. The proposed model is also applicable to various other fields where reversible logic is utilized, such as low-power computing, fault-tolerant designs, and DNA computing. In addition, our model can be applied to network-based problems, such as logistics distribution and time-stage network problems.

Fidelity of noisy multiple-control reversible gates

The effect of frequency noise on correct operation of the multiple-control Toffoli, Fredkin, and Peres gates has been discussed. In the framework of the Ising model, the energy spectrum of a chain of atoms with nuclear spins one-half in a spinless semiconductor matrix has been obtained, and allowed transitions corresponding to the operation algorithm of these gates have been determined. The fidelities of the obtained transitions were studied depending on the number of control qubits and parameters of the radio-frequency control pulses. It has been shown that correct operation of the Toffoli and Fredkin gates does not depend on the number of control qubits, while the Peres gate fidelity decreases significantly with the increasing number of control signals. The calculated ratios of the Larmor frequency to the exchange interaction constant correspond with the results of other studies.

Parallel entangling operations on a universal ion-trap quantum computer.

The circuit model of a quantum computer consists of sequences of gate operations between quantum bits (qubits), drawn from a universal family of discrete operations1. The ability to execute parallel entangling quantum gates offers efficiency gains in numerous quantum circuits2-4, as well as for entire algorithms-such as Shor's factoring algorithm5-and quantum simulations6,7. In circuits such as full adders and multiple-control Toffoli gates, parallelism can provide an exponential improvement in overall execution time through the divide-and-conquer technique8. More importantly, quantum gate parallelism is essential for fault-tolerant error correction of qubits that suffer from idle errors9,10. However, the implementation of parallel quantum gates is complicated by potential crosstalk, especially between qubits that are fully connected by a common-mode bus, such as in Coulomb-coupled trapped atomic ions11,12 or cavity-coupled superconducting transmons13. Here we present experimental results for parallel two-qubit entangling gates in an array of fully connected trapped 171Yb+ ion qubits. We perform a one-bit full-addition operation on a quantum computer using a depth-four quantum circuit4,14,15, where circuit depth denotes the number of runtime steps required. Our method exploits the power of highly connected qubit systems using classical control techniques and will help to speed up quantum circuits and achieve fault tolerance in trapped-ion quantum computers.

Computational analysis and comparison of reversible gates for design and test of logic circuits

ABSTRACTQuantum computing is one of the most significant anticipation towards the accomplishment of interminable consumer demands of small, high speed, and low-power operable electronics devices. As reversible logic circuits have direct applicability to quantum circuits, design and synthesis of these circuits are finding grounds for emerging nano-technologies of quantum computing. Multiple Controlled Toffoli (MCT) and Multiple Controlled Fredkin (MCF) are the fundamental reversible gates that playing key role in this phase of development. A number of special reversible gates have also been presented so far, which were claimed superior for providing certain purposes like logic development and testing. This paper critically analyses a range of these gates to procure an optimal solution for design, synthesis and testing of reversible circuits. The experimentation is facilitated at three subsequent levels, i.e. gates properties, quantum cost and design & testability. MCT and MCF gates are found up to 50% more cost-effective than special gates at design level and 34.4% at testability level. Maximum reversibility depth (MRD) is included as a new measurement parameter for comparison. Special gates exhibit MRD up to 7 which ideally should be 1 for a system to be physically reversible as that of MCT and MCF gates.

Simplification and modification of multiple controlled Toffoli circuits for testability

Testability dramatically enhances the operating cost in reversible logic circuits as it increases the cost metrics such as gate count, quantum cost, number of wires and garbage output. This increase also affects the utilization of resources, which further enhances overall cost of testing. This paper presents a new design for testability methodology for reversible circuits by exploring the properties of multiple controlled Toffoli and Fredkin gates, to produce online testable circuits at lower cost metrics. The method includes simplification and modification of Toffoli circuits to form parity-preserving Toffoli–Fredkin cascades. The testability in these cascades can be achieved by comparing the parity of inputs and outputs using controlled-NOT gates on an additional wire. Single-point failures in reversible logic circuits are targeted by means of detecting bit faults. In contrast to the existing work, the present model is robust, low cost and has lesser design complexity. Experiments are conducted on a set of benchmark circuits to prove the efficacy of the present work. The results show an average reduction by 15.9 % in gate cost and 11.0 % in total operating cost when compared to the most recent existing work formulated on the same platform.

Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates

Reversible logic has 100% fault observability meaning that a fault in any circuit node propagates to the output stage. In other words, reversible circuits are latent-fault-free. Our motivation is to incorporate this unique feature of reversible logic to design CMOS circuits having perfect or 100% Concurrent Error Detection (CED) capability. For this purpose, we propose a new fault preservative reversible gate library called Even Target - Mixed Polarity Multiple Control Toffoli (ET-MPMCT). By using ET-MPMCT, we ensure that the evenness/oddness of applied 1’s at input, is preserved at all levels of a circuit including output level unless there is a faulty node. A single fault always destroys the parity of input at the output. Our design strategy has two steps for a given function: 1) implement the function with our proposed reversible ET-MPMCT gate library; and 2) apply reversible-to-CMOS gate conversion. For the first step, we propose two approaches. For our first approach in step 1, we first need to have a reversible form of the given function if it is irreversible. Then, synthesize the reversible function using Mixed Polarity Multiple Control Toffoli (MPMCT) gate library by conventional reversible logic synthesis techniques. Finally, the synthesized circuit is converted to ET-MPMCT constructed circuit which is fault preservative. Our second approach, is an ESOP - Exclusive Sum of Products - based synthesis approach modified for our proposed fault preservative ET-MPMCT gate library. It does work with both irreversible and reversible functions. We synthesize our circuits with both approaches in step 1 and choose the circuit with lower number of reversible gates to be fed to step 2 of our design strategy. In second step of our design strategy, we convert our fault preservative reversible circuits into their CMOS counterparts. The performance of our designs is compared with other CED schemes in the literature in terms of area, power consumption, delay and detection rate. Simulations are done with Cadence Genus tool using TSMC 40nm technology. Clearly, results are in favor of our proposed techniques.

Design for Stuck-at Fault Testability in MCT based Reversible Circuits

Testability leads to a large increment in operating costs from their original circuits which drastically increases the power consumption in logic circuits. This paper presents a new design for testability methodology for the detection of stuck-at faults in multiple controlled Toffoli based reversible circuits. The circuit is modified in such a manner that the applied test vector reaches all the levels without any change in values on the wires of the circuit. An (n+1) dimensional general test set containing only two test vectors is presented, which provide full coverage of single and multiple stuck-at faults in the circuit. The work is further extended to locate the occurrence of stuck-at faults in the circuit. Deterministic approaches are described and the modification methodology is experimented on a set of benchmarks. The present work achieved a reduction up to $50.58\%$ in operating costs as compared to the existing work implemented on the same platform.

Mapping from multiple-control Toffoli circuits to linear nearest neighbor quantum circuits

In recent years, quantum computing research has been attracting more and more attention, but few studies on the limited interaction distance between quantum bits (qubit) are deeply carried out. This paper presents a mapping method for transforming multiple-control Toffoli (MCT) circuits into linear nearest neighbor (LNN) quantum circuits instead of traditional decomposition-based methods. In order to reduce the number of inserted SWAP gates, a novel type of gate with the optimal LNN quantum realization was constructed, namely NNTS gate. The MCT gate with multiple control bits could be better cascaded by the NNTS gates, in which the arrangement of the input lines was LNN arrangement of the MCT gate. Then, the communication overhead measurement model on inserted SWAP gate count from the original arrangement to the new arrangement was put forward, and we selected one of the LNN arrangements with the minimum SWAP gate count. Moreover, the LNN arrangement-based mapping algorithm was given, and it dealt with the MCT gates in turn and mapped each MCT gate into its LNN form by inserting the minimum number of SWAP gates. Finally, some simplification rules were used, which can further reduce the final quantum cost of the LNN quantum circuit. Experiments on some benchmark MCT circuits indicate that the direct mapping algorithm results in fewer additional SWAP gates in about 50%, while the average improvement rate in quantum cost is 16.95% compared to the decomposition-based method. In addition, it has been verified that the proposed method has greater superiority for reversible circuits cascaded by MCT gates with more control bits.

Exploiting Reversible Computing for Latent-Fault-Free Error Detecting/Correcting CMOS Circuits

Unlike conventional CMOS circuits, reversible circuits do not have latent faults, so faults occurring in internal circuit nodes always result in an error at the output. This is a unique feature for online or concurrent fault tolerance and the main motivation of this paper with an aim of achieving highly efficient fault-tolerant CMOS logic circuits. For this purpose, we first implement fault-tolerant reversible circuits. We develop two techniques to make a reversible circuit fault-tolerant by using multiple-control Toffoli gates. The first technique is based on single parity preserving and offers error detection for odd number of errors at the output. The second technique is constructed on Hamming codes, which results in circuits detecting any number of errors unless the number of errors at the output is the order of $d$ or correcting $(d-1)/2$ bit errors, where $d$ is the minimum Hamming distance between any pair of bit patterns. We select $d=3$ in this paper. We also claim that 100% error detection is possible with conservative reversible gates, such as a Fredkin gate. For this purpose, we develop a greedy synthesis algorithm that implements an arbitrary reversible function with multiple-control Fredkin gates. As the next step, we utilize the proposed reversible circuits with conventional CMOS gates. This certainly approves the practical use of the proposed techniques. The effectiveness of our techniques is demonstrated on benchmark circuits, implemented by both reversible and CMOS gates, in terms of fault tolerance performances and area costs. Comparisons with the related studies in the literature as well as with dual-modular redundancy and triple-modular redundancy-based circuits clearly favor the proposed designs.

Advantages of using relative-phase Toffoli gates with an application to multiple control Toffoli optimization

Various implementations of the Toffoli gate up to a relative phase have been known for years. The advantage over regular Toffoli gate is their smaller circuit size. However, their use has been often limited to a demonstration of quantum control in designs such as those where the Toffoli gate is being applied last or otherwise for some specific reasons the relative phase does not matter. It was commonly believed that the relative phase deviations would prevent the relative phase Toffolis from being very helpful in practical large-scale designs. In this paper, we report three circuit identities that provide the means for replacing certain configurations of the multiple control Toffoli gates with their simpler relative phase implementations, up to a selectable unitary on certain qubits, and without changing the overall functionality. We illustrate the advantage via applying those identities to the optimization of the known circuits implementing multiple control Toffoli gates, and report the reductions in the CNOT-count, T-count, as well as the number of ancillae used. We suggest that a further study of the relative phase Toffoli implementations and their use may yield other optimizations.