An Algorithm for Reversible Logic Circuit Synthesis Based on Tensor Decomposition

Abstract

An algorithm for reversible logic synthesis is proposed. The task is, for a given n -bit substitution map, to find a sequence of reversible logic gates that implements the map. The gate library adopted in this work consists of multiple-controlled Toffoli gates with m control bits, where m ∈ {0, …, n − 1}. Controlled gates with large m (> 2) are then further decomposed into smaller gates ( m ≤ 2). A primary goal in designing the algorithm is to reduce the number of Toffoli gates which is known to be universal. The main idea is to view an n -bit substitution map as a rank-2 n tensor, and to transform it such that the resulting map can be written as a tensor product of a rank-(2 n − 2) tensor and the 2 × 2 identity matrix. It can then be seen that the transformed map acts nontrivially on n − 1 bits only, meaning that the map to be synthesized becomes ( n − 1)-bit substitution. This size reduction process is iteratively applied until it reaches a tensor product of only 2 × 2 matrices. The time complexity of the algorithm is exponential in n as most previously known heuristic algorithms for reversible logic synthesis are, but it terminates within reasonable time for not too large n which may find practical uses. As stated earlier, our primary target is to reduce the number of Toffoli gates in the output circuit. Benchmark results show that the algorithm works well for hard benchmark functions, but it does not seem advantageous when the function is structured. As an application, the algorithm is applied to find reversible circuits for cryptographic substitution boxes, which are often required in quantum cryptanalysis.