Multiple Code Rates Research Articles

End-to-end learning of adaptive coded modulation schemes for resilient wireless communications

Adaptive modulation and coding schemes play a crucial role in ensuring robust data transfer in wireless communications, especially when faced with changes or interference in the transmission channel. These schemes involve the use of variable coding rates, which can be achieved normally through code puncturing or shortening, and have been adopted in 4G and 5G communication standards. In recent works, auto-encoders for wireless communications have demonstrated the ability to learn short code representations that achieve gains over conventional codes. Such a methodology is attractive as it can learn optimal representations under a variety of channel conditions. However, due to its structure the auto-encoder does not currently support multiple code rates with a single model. This article draws upon the discipline of multi-task learning, as it applies to deep learning and therefore devises a branching architecture for the auto-encoder and custom training algorithm in training transmitter and receiver for adaptive modulation and coding. In this article we aim to demonstrate improvements in Block Error Rate over conventional methods in the Additive White Gaussian Noise channel, and to analyse the performance of the model under Rayleigh fading channels without retraining the auto-encoder on the new channel. This article demonstrates a novel approach towards training auto-encoder models to jointly learn adaptive modulation and coding schemes framed as a multi-task learning problem. The research outcomes extend end-to-end learning approaches to the design of adaptive wireless communications systems.

Design and Implementation of a 6.5-Gb/s Multiradix Simplified Viterbi-Sphere Decoder for Trellis-Coded Generalized Spatial Modulation With Spatial Multiplexing

A simplified Viterbi-sphere decoder (VSD) for trellis-coded generalized spatial modulation (GSM) with spatial multiplexing (TCGSMX) is designed and implemented to exploit the soft information for achieving better performance. Multiple code rates are supported to combat different levels of spatial correlations in fading channels and to offer options for various transmission efficiencies. Hence, the proposed multiradix simplified VSD is configurable to process four radix-2 stages for 1/2 code rate, two radix-4 stages for 2/3 code rate, and one radix-8 stage for 3/4 code rate in one clock cycle to upgrade the throughput by fully pipelined architecture. To reduce the complexity, several techniques are employed, including the efficient settings of survival nodes of sphere decoding and sequence length for backtracing by Viterbi decoding. The chip has been fabricated in TSMC 40-nm CMOS technology. Compared to related works, the implementation provides higher throughput up to 6.5 Gb/s at 1.1-V supply voltage as well as 180.8-MHz operating frequency and consumes 374.3 mW for TCGSMX systems using 16-QAM and code rate of 1/2.

A Universal Efficient Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders

Quasi-cyclic low-density parity-check (QC-LDPC) codes for modern communication standards usually have multiple code rates and block lengths. Therefore, reconfigurable LDPC decoders have received widespread attention, which require circular-shift networks to support various expansion factors. Besides, for inputs smaller than the network size, the circular-shift network is desired to process multiple frames in parallel to maximize hardware utilization efficiency. The increasing demands put severe challenges to low-complexity implementations of shift networks, especially for codes with numerous expansion factors, such as 5G LDPC codes. In this brief, we present a universal design of efficient reconfigurable circular-shift networks. Through an ingenious modification on the order of permutations, the generation of control signals is considerably simplified, leading to a significant reduction of area and critical path. Moreover, a hybrid architecture organically integrating different networks is proposed for further complexity reduction. Implementation results under TSMC 90 nm technology demonstrate that the proposed network can achieve 25% area reduction and 46% area-efficiency (AE) improvement over the state-of-the-art ones.

On the Design of Channel Coding Autoencoders With Arbitrary Rates for ISI Channels

This letter presents an autoencoder-based channel coding scheme in the presence of inter-symbol interference (ISI) and additive white Gaussian noise (AWGN), supporting arbitrary coding rates. Both the transmitter and receiver of the proposed autoencoder employ bi-directional gated recurrent unit (Bi-GRU) layers. Additional extra dense layers are applied at the end of the transmitter and at the beginning of the receiver, serving as learnable puncture and depuncture modules, respectively. Different code rates can be achieved by adjusting the output dimension of the extra dense layers. Experimental results demonstrate that the proposed autoencoder significantly outperforms conventional convolutional codes over ISI channels, for multiple code rates. The proposed autoencoder also outperforms LDPC codes in the low signal-to-noise ratio (SNR) regime. The neural codes still require improvement to be competitive in the high SNR regime.

Private Information Retrieval From a Cellular Network With Caching at the Edge

We consider the problem of downloading content from a cellular network that is cached at the wireless edge while achieving privacy. In particular, we consider private information retrieval (PIR) of content from a library of files, i.e., the user wishes to download a file and does not want the network to learn any information about which file she is interested in. To reduce the backhaul usage, content is cached at the wireless edge in a number of small-cell base stations (SBSs) using maximum distance separable codes. We propose a PIR scheme based on generalized Reed–Solomon codes for this scenario that achieves privacy against a number of spy SBSs that collaborate. The proposed PIR scheme is an extension of a scheme by Kumar et al. to the case of multiple code rates, suitable for the scenario where files have different popularities. We derive the backhaul rate and optimize the content placement to minimize it. We prove that uniform content placement is optimal, i.e., all files that are cached should be stored using the same code rate. This is in contrast to the case where no PIR is required. Furthermore, we show numerically that popular content placement is optimal for some scenarios.

Progressive Matrix Growth Algorithm for Constructing Rate-Compatible Length-Scalable Raptor-Like Quasi-Cyclic LDPC Codes

With the worldwide deployment and rapid development of digital television terrestrial broadcasting (DTTB) systems, the demands of diversified multimedia services from the fixed/mobile receptions increase significantly. To satisfy the various requirements of quality of service, the forward error correction codes with multiple code rates and lengths become a trend for DTTB standards. In this paper, rate-compatible length-scalable raptor-like quasi-cyclic low density parity check (RL-QC-LDPC) codes are proposed for future DTTB systems, where a wide range of code rates and information/parity block lengths can be obtained with low implementation complexity. A low-complexity construction method, called progressive matrix growth (PMG), is also proposed for such kind of RL-QC-LDPC codes. Unlike conventional construction methods, PMG performs 2-D progressive extension of both information variable nodes and check nodes with limited computational complexity and memory resources. Based on the performance prediction provided by the tool of multi-edge type density evolution, several code families are constructed with PMG as examples, and careful discussions on design parameters are given. The numerical results show that the average gaps of SNR threshold to Shannon limit of binary-input additive white Gaussian noise channel are only 0.41~0.44 dB for the code families with information-bit puncturing.

Rate-Adaptive Protograph LDPC Codes for Multi-Level-Cell NAND Flash Memory

The multi-level-cell (MLC) NAND flash memory exhibits a diversity of the raw bit error rate (BER) over different program/erase (P/E) cycles and different types of bits within a memory cell. In this letter, we first apply a protograph-based extrinsic information transfer chart analysis to the MLC flash channel and design novel rate-adaptive protograph low-density parity-check (RAP-LDPC) codes by using a code extension approach. The proposed RAP-LDPC code has multiple code rates, which can be adapted dynamically to different P/E cycles. To mitigate the unbalanced raw BERs between different types of bits within a memory cell, we further propose an optimum mapping between the variable nodes of the protograph and different types of bits of the memory cell. Since the proposed RAP-LDPC codes are based on the same parity-check matrix with specific structure, a single protograph encoder/decoder is sufficient to handle all the code rates. Simulation results demonstrate that the proposed RAP-LDPC codes with optimum mapping outperform the irregular LDPC codes for all the code rates with a faster decoding convergence speed for the MLC flash channel.

QFEC ASIP: A Flexible Quad-Mode FEC ASIP for Polar, LDPC, Turbo, and Convolutional Code Decoding

In this paper, we extend polar decoding function to our previous design, and propose a flexible quad-mode forward error correction application specific instruction-set processor (QFEC ASIP) that supports polar, low-density parity-check (LDPC), turbo, and convolutional code (CC) decoding with multiple code lengths and code rates. A unified polar/LDPC/turbo/CC quad-mode algorithm framework is presented. The top level architecture of QFEC ASIP and the polar data path are designed on the basis of the algorithm framework. A quad-mode confliction-free global memory system is proposed. 65.2% of global memory banks, 48.9% of global memory bits, and 29.7% of global memory area are saved via hardware sharing. Specially accelerated FEC decoding instructions make the decoding procedure fully programmable and ensure the high throughput. Synthesis using 65-nm technology shows that the total area of QFEC ASIP is 4.26 mm2. QFEC ASIP provides the maximum throughput of 1345 Mb/s for polar, 917 Mb/s for LDPC (WiMAX), 320 Mb/s for turbo, and 387 Mb/s for CC (64 states) at the clock frequency of 344 MHz. QFEC ASIP occupies much smaller silicon area than the sum of the silicon area of 4 single-mode FEC decoders that together provide a similar function range as QFEC ASIP.

Multiple‐rate codes from block Markov superposition transmission of first‐order Reed–Muller and extended Hamming codes

Block Markov superposition transmission (BMST) of first-order Reed–Muller and extended Hamming (RMEH) codes is investigated. Multiple code rates can be easily realised by adjusting the mixture ratio of Reed–Muller and extended Hamming codes. Compared with the original BMST of repetition and single-parity-check (RSPC) codes, the proposed BMST-RMEH codes can perform close to Shannon limits over a wide range of code rates with about only half the encoding memories of BMST-RSPC codes. As a result of the reduction of encoding memories, the decoding complexity and delay of BMST-RMEH codes are approximately half (or even lower than) those of BMST-RSPC codes.

Multi-Mode Unrolled Architectures for Polar Decoders

In this work, we present a family of architectures for polar decoders using a reduced-complexity successive-cancellation decoding algorithm that employs unrolling to achieve extremely high throughput values while retaining moderate implementation complexity. The resulting fully-unrolled, deeply-pipelined architecture is capable of achieving a coded throughput in excess of 1 Tbps on a 65 nm ASIC at 500 MHz-three orders of magnitude greater than current state-of-the-art polar decoders. However, unrolled decoders are built for a specific, fixed code. Therefore we also present a new method to enable the use of multiple code lengths and rates in a fully-unrolled polar decoder architecture. This method leads to a length- and rate-flexible decoder while retaining the very high speed typical to unrolled decoders. The resulting decoders can decode a master polar code of a given rate and length, and several shorter codes of different rates and lengths. We present results for two versions of a multi-mode decoder supporting eight and ten different polar codes, respectively. Both are capable of a peak throughput of 25.6 Gbps. For each decoder, the energy efficiency for the longest supported polar code is shown to be of 14.8 pJ/bit at 250 MHz and of 8.8 pJ/bit at 500 MHz.

Multi‐standard high‐throughput and low‐power quasi‐cyclic low density parity check decoder for worldwide interoperability for microwave access and wireless fidelity standards

This study presents a reconfigurable quasi-cyclic low density parity check (QC-LDPC) decoder for IEEE 802.16e worldwide interoperability for microwave access and IEEE 802.11n wireless fidelity communication standards. It supports multiple code-rates of 1/2, 2/3, 3/4, 5/6 and its architecture has been designed based on column layered decoding technique to enhance the convergence speed. The authors have suggested a register file based approach to handle the shift property of the modified parity check matrix and a modified version of the matrix permutation method has been introduced to reduce the number of check nodes which handle multiple messages. In addition, parallel processing has been incorporated in the decoder architecture to attain higher achievable throughput. This QC-LDPC decoder is implemented in 90 nm CMOS process and is post-layout simulated. It can achieve a throughput of 796 Mbps for a code-rate of 5/6. With 0.9 V supply, it consumes 146 mW of total power at 149 MHz clock frequency.

High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule

This paper presents architecture of block-level-parallel layered decoder for irregular LDPC code. It can be reconfigured to support various block lengths and code rates of IEEE 802.11n (WiFi) wireless-communication standard. We have proposed efficient comparison techniques for both column and row layered schedule and rejection-based high-speed circuits to compute the two minimum values from multiple inputs required for row layered processing of hardware-friendly min-sum decoding algorithm. The results show good speed with lower area as compared to state-of-the-art circuits. Additionally, this work proposes dynamic multi-frame processing schedule which efficiently utilizes the layered-LDPC decoding with minimum pipeline stages. The suggested LDPC-decoder architecture has been synthesized and post-layout simulated in 90 nm-CMOS process. This decoder occupies 5.19 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area and supports multiple code rates like 1/2, 2/3, 3/4 & 5/6 as well as block-lengths of 648, 1296 & 1944. At a clock frequency of 336 MHz, the proposed LDPC-decoder has achieved better throughput of 5.13 Gbps and energy efficiency of 0.01 nJ/bits/iterations, as compared to the similar state-of-the-art works.

A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications

This paper presents the first silicon-proven stochastic LDPC decoder to support multiple code rates for IEEE 802.15.3c applications. The critical path is improved by a reconfigurable stochastic check node unit (CNU) and variable node unit (VNU); therefore, a high throughput scheme can be realized with 768 MHz clock frequency. To achieve higher hardware and energy efficiency, the reduced complexity architecture of tracking forecast memory is experimentally investigated to implement the variable node units for IEEE 802.15.3c applications. Based on the properties of parity check matrices and stochastic arithmetic, the optimized routing networks with re-permutation techniques are adopted to enhance chip utilization. Considering the measurement uncertainties, a delay-lock loop with isolated power domain and a test environment consisting of an encoder, an AWGN generator and bypass circuits are also designed for inner clock and information generation. With these features, our proposed fully parallel LDPC decoder chip fabricated in 90-nm CMOS process with 760.3 K gate count can achieve 7.92 Gb/s data rate and power consumption of 437.2 mW under 1.2 V supply voltage. Compared to the state-of-the-art IEEE 802.15.3c LDPC decoder chips, our proposed chip achieves over 90% reduction of routing wires, 73.8% and 11.5% enhancement of hardware and energy efficiency, respectively.

Trading Regeneration and Spectrum Utilization in Code-Rate Adaptive Flexi-Grid Networks

Introduced to improve the spectral efficiency, time-frequency packing technique allows the exploitation of different code rates, leading to different levels of spectral utilization and all-optical reach. To ensure quality of transmission of the optical signal, opto-electronic regeneration must be used to propagate the transmission beyond the maximum optical reach and can inherently offer conversion of spectrum and code rate. In this way, multiple code rates can be enabled in optical networks, leading to a flexible design in which spectrum utilization and regeneration can be properly optimized and traded. This paper addresses for the first time the joint problem of selecting the code rate, the regeneration nodes, the spectrum allocation and the route for the requested lightpaths in an optical network with a flexi-grid. A genetic algorithm is proposed that balances the contrasting objectives of minimizing the regeneration nodes and the spectrum utilization. Results show that when regeneration nodes are minimized, code-rate adaptation is able to reduce the regeneration nodes as well as the spectrum utilization with respect to rate-fixed optical networks. In general, a balance of the two contrasting objectives is preferred to achieve a low resource utilization.

A Low Complexity-High Throughput QC-LDPC Encoder

This paper introduces hardware architectures for encoding Quasi-Cyclic Low-Density Parity Check (QC-LDPC) codes. The proposed encoders are based on appropriate factorization and subsequent compression of involved matrices by means of a novel technique, which exploits features of recursively-constructed QC-LDPC codes. The particular approach derives to linear encoding time complexity and requires a constant number of clock cycles for the computation of parity bits for all the constructed codes of various lengths that stem from a common base matrix. The proposed architectures are flexible, as they are parameterized and can support multiple code rates and codes of different lengths simply by appropriate initialization of memories and determination of data bus widths. Implementation results show that the proposed encoding technique is more efficient for some LDPC codes than previously proposed solutions. Both serial and parallel architectures are proposed. Hardware instantiations of the proposed serial encoders demonstrate high throughput with low area complexity for code words of many thousand bits, achieving area reduction compared to prior art. Furthermore, parallelization is shown to efficiently support multi-Gbps solutions at the cost of moderate area increase. The proposed encoders are shown to outperform the current state-of-the-art in terms of throughput-area-ratio and area-time complexity by 10 to up to 80 times for codes of comparable error-correction strength.

Low-complexity iteration control algorithm for multi-rate partially parallel layered LDPC decoders

Concurrent partially parallel syndrome computation reduces complexity but incurs increased error rates due to the hard decision flipping (HDF) problem. Proposed is a low-complexity iteration control algorithm (LC-ICA) that eliminates BER degradation. The HDF rate is also used to terminate undecodable blocks to further save iterations. The algorithm works over multiple code rates. The implementation results show that a six-rate LC-ICA requires only 23.32% of a single-rate fully-parallel syndrome hardware.

Joint Scheduling and Resource Allocation in the OFDMA Downlink: Utility Maximization Under Imperfect Channel-State Information

We consider the problem of simultaneous user-scheduling, power-allocation, and rate-selection in an orthogonal frequency division multiple access (OFDMA) downlink, with the goal of maximizing expected sum-utility under a sum-power constraint. In doing so, we consider a family of generic goodput-based utilities that facilitate, e.g., throughput-based pricing, quality-of-service enforcement, and/or the treatment of practical modulation-and-coding schemes (MCS). Since perfect knowledge of channel state information (CSI) may be difficult to maintain at the base-station, especially when the number of users and/or subchannels is large, we consider scheduling and resource allocation under imperfect CSI, where the channel state is described by a generic probability distribution. First, we consider the “continuous” case where multiple users and/or code rates can time-share a single OFDMA subchannel and time slot. This yields a nonconvex optimization problem that we convert into a convex optimization problem and solve exactly using a dual optimization approach. Second, we consider the “discrete” case where only a single user and code rate is allowed per OFDMA subchannel per time slot. For the mixed-integer optimization problem that arises, we discuss the connections it has with the continuous case and show that it can solved exactly in some situations. For the other situations, we present a bound on the optimality gap. For both cases, we provide algorithmic implementations of the obtained solution. Finally, we study, numerically, the performance of the proposed algorithms under various degrees of CSI uncertainty, utilities, and OFDMA system configurations. In addition, we demonstrate advantages relative to existing state-of-the-art algorithms.

Generic Permutation Network for QC-LDPC Decoder

Permutation network plays an important role in the reconfigurable QC-LDPC decoder for most modem wireless communication systems with multiple code rates and various code lengths. This paper presents the generic permutation network (GPN) for the reconfigurable QC-LDPC decoder. Compared with conventional permutation networks, this proposal could break through the input number restriction, such as power of 2 and other limited number, and optimize the network for any application in demand. Moreover, the proposed scheme could greatly reduce the latency because of less stages and efficient control signal generating algorithm. In addition, the proposed network processes the nature of high parallelism which could enable several groups of data to be cyclically shifted simultaneously. The synthesis results using the 90 nm technology demonstrate that this architecture can be implemented with the gate count of 18.3k for WiMAX standard at the frequency of 600 MHz and 10.9k for WiFi standard at the frequency of 800 MHz.

Low-Complexity Switch Network for Reconfigurable LDPC Decoders

In this paper, we propose an efficient low-complexity switch network design for reconfigurable low-density parity-check (LDPC) decoders. The proposed architecture leads to significant reductions in hardware complexity. Since the structured quasi-cyclic (QC) LDPC codes for most modern wireless communication systems include multiple code rates, various block lengths, and different sizes of submatrices, a reconfigurable LDPC decoder is desirable and the barrel shifter needs to be programmable. The Benes network cannot be optimized as the barrel shifter for a reconfigurable LDPC decoder when the input size of barrel shifter is not a power of 2. Also, it is not trivial to generate all the control signals on-the-fly for numerous 2 × 2 switches in the switch network. In this paper, a novel low-complexity switch network design is proposed, which can be used efficiently when the input size of barrel shifters is not a power of 2. Furthermore, we propose a novel algorithm to generate all the control signals, which can be implemented with a small size of lookup table (LUT) or a simple combination logic on-the-fly, using the properties that both the full-size switch network can be broken into two half-size switch networks and the barrel shifters for the structured QC LDPC decoders require only cyclic shifts. Compared with conventional Benes networks using a dedicated LUT or a complicated signal generating algorithm, the proposed architectures achieve significant hardware reductions in implementing the barrel shifters for reconfigurable LDPC decoders. In synthesis result using the TSMC 0.18-¿m standard cell CMOS technology, the proposed switch network for a reconfigurable LDPC decoder of IEEE 802.16e and IEEE 802.11n can be implemented with an area of 0.772 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , which leads to a significant area reduction.

Permutation Network for Reconfigurable LDPC Decoder Based on Banyan Network

Since the structured quasi-cyclic low-density parity-check (QC-LDPC) codes for most modern wireless communication systems include multiple code rates, various block lengths, and the corresponding different sizes of submatrices in parity check matrix (PCM), the reconfigurable LDPC decoder is desirable and the permutation network is needed to accommodate any input number (IN) and shift number (SN) for cyclic shift. In this paper, we propose a novel permutation network architecture for the reconfigurable QC-LDPC decoders based on Banyan network. We prove that Banyan network has the nonblocking property for cyclic shift when the IN is power of 2, and give the control signal generating algorithm. Through introducing the bypass network, we put forward the nonblocking scheme for any IN and SN. In addition, we present the hardware design of the control signal generator, which can greatly reduce the hardware complexity and latency. The synthesis results using the TSMC 0.18 μm library demonstrate that the proposed permutation network can be implemented with the area of 0.546 mm 2 and the frequency of 292 MHz.