Multiple Bits Research Articles

An energy-efficient cache replacement policy for ultra-dense racetrack memory

Racetrack memory (RTM) based caches provide improved energy and area efficiencies compared to traditional SRAM caches via multi-bit storage capability. The RTM cell arranges multiple bits in a magnetic nanowire track and is equipped with a shared port to access the data. Accessing a bit necessitates to shift the bit under the port. Since the serial access nature of the RTM cell induces energy penalty, it is crucial to reduce the number of shifts. To do so, we have devised an energy-efficient cache replacement policy that first calculates the shift cost of a group of rarely reused cache lines in a cache set. After that, it chooses a victim cache line from that group that incurs minimum shift cost. Employing 1MB RTM cache for single-programmed workloads, the proposed policy outperforms the state-of-the-art by 23.2% and 48.8% in terms of energy consumption and shift cost respectively. For multi-programmed workloads, the energy saving and shift improvement translates to 22.8% and 39.8% respectively using 4MB RTM shared cache.

Linear Cryptanalysis of Reduced-Round Simeck Using Super Rounds

The Simeck family of lightweight block ciphers was proposed by Yang et al. in 2015, which combines the design features of the NSA-designed block ciphers Simon and Speck. Previously, we proposed the use of linear cryptanalysis using super-rounds to increase the efficiency of implementing Matsui’s second algorithm and achieved good results on all variants of Simon. The improved linear attacks result from the observation that, after four rounds of encryption, one bit of the left half of the state of the cipher depends on only 17 key bits (19 key bits for the larger variants of the cipher). We were able to follow a similar approach, in all variants of Simeck, with an improvement in Simeck 32 and Simeck 48 by relaxing the previous constraint of a single active bit, using multiple active bits instead. In this paper we present improved linear attacks against all variants of Simeck: attacks on 19-rounds of Simeck 32/64, 28-rounds of Simeck 48/96, and 34-rounds of Simeck 64/128, often with the direct recovery of the full master key without repeating the attack over multiple rounds. We also verified the results of linear cryptanalysis on 8, 10, and 12 rounds for Simeck 32/64.

IADC Code Upgrade: PDC Bit and BHA Forensics Using Rig-Based Photographic Documentation Practices

Summary This paper establishes uniform recommended industry practices for photo documentation of polycrystalline diamond compact (PDC) bits and bottomhole assemblies (BHAs). These recommended practices were developed by a subcommittee of the joint International Association of Drilling Contactors (IADC)/Society of Petroleum Engineers (SPE) industry in an effort to upgrade the IADC dull grading practices. Effective field photographic documentation and training to identify the causes of damage enables the team to modify parameters used and make other immediate changes in the BHA/drilling system with a higher degree of confidence that they will increase drill rate or extend bit life. The field documentation also provides the basis for more detailed post-drill shop grading and extensive redesign, if needed. The recommended photographic documentation consists of a specific set of photos of each blade, a top view, a side view, and views of each contact point in the BHA (i.e., kick pads, stabilizer blades, and reamers). It is common for rigsite teams to take photos of bits pulled, but these have not historically provided the detail required to distinguish one potential cause from another. There are proven changes in practices or BHA configuration that can be made to mitigate each type of dysfunction, but this cannot occur unless the cause is identified correctly. Appropriate photographic documentation, when coupled along with an understanding of the different PDC cutter and bit damage mechanisms which may occur, enables the rigsite team to identify the dysfunction and implement the changes needed. While other data sources, such as digital drilling data, should be analyzed to estimate the event timing and confirm the cause, the damage that is observed in the photographic documentation plays a critical role in directing the actual redesign effort. For example, downhole accelerometer data may indicate the presence of BHA whirl, but whether this damages the bit in a given situation is dependent on formation hardness and other factors. Whirl may not be the priority of redesign unless the photographic documentation shows a pattern of damage that is known to be specifically due to BHA whirl. These photographic documentation practices were developed specifically to support drilling forensics. The guidelines were compiled from the practices of multiple operators, bit manufacturers, and service companies with significant experience in utilizing similar photographic documentation to support timely rigsite decisions. The photographic documentation is not complex and experience has shown that within a short period of training and daily discussions, the collection of high-quality photos becomes a routine, sustainable practice. To obtain the greatest value from photographic documentation, operators must also develop training for field personnel in how to recognize the dysfunction that caused the damage. This document is intended to both standardize field photographic documentation practices and provide training material appropriate for field personnel on how to suitably document bit and BHA components using photos.

Programming metastable transition sequences in digital mechanical materials

The realization of unconventional computing methods in soft matter has inspired the creation of mechanological systems capable of processing information. These systems often utilize bistable mechanisms that serve as mechanically abstracted bits to perform digital logic operations. Yet, the input of such operations often requires manual control of complex cyclic loading to reach a desired configuration. This research presents a method to design digital mechanical materials that can enter a programmable sequence of metastable configurations through simple displacement-controlled inputs. Interactions between serially connected bistable units enable the transition and reset behavior of mechanical bits. An analytical model using the principle of minimum total potential energy of a single bit is presented to articulate systematic ways to tune the critical force thresholds and displacements of metastable transition sequences. This work elucidates how the application of a prescribed displacement allows for novel resetting behavior that enables simultaneous transitions of multiple bits. By combining the principles of deterministic transition sequences and mechanical computing, a mechanical analog to digital conversion (ADC) material system is introduced that digitizes a continuous force stimulus into binary configurations that perform computations within the mechanical material based on the applied load. The mechanical ADC establishes a foundation for the integration of environmental sensing, information processing, and response in a soft material system.

3-bit Shift Register Using QCA Nanotechnology

Background:: Quantum-dot Cellular Automata (QCA) is a new emerging nanotechnology that has been proven to be an improved alternative to complementary metal oxide semiconductor (CMOS) technology. It consists of a group of cells that can perform computational functions when combined and arranged in a particular manner. Objective:: The Flip-Flops are widely affiliated with the circuits of logical and arithmetic unit structures that are used for the processors. Data (D) Flip-Flop is the most important and widely used Flip-Flop among all different types due to its better performance and efficiency. Hence, an efficient D Flip-Flop needs to be developed using QCA nanotechnology. Method:: This paper proposes a new design for D Flip-Flop in QCA nanotechnology. The proposed D Flip-Flop has 28 quantum cells and covers an area of 0.03 μm2 . Furthermore, the paper presents a new design for a 3-bit Shift Register using the proposed D Flip-Flops in QCA nanotechnology keeping in mind the importance of the same in storing and transferring multiple bits of data. Result:: The proposed D Flip-Flop and the 3-bit Shift Register are compared with the existing QCAbased designs. The proposed Shift Register has 100 quantum cells and covers an area of 0.11 μm2 . Conclusion:: The comparison concludes that the proposed D Flip-Flop and the 3-bit Shift Register have used a lesser number of QCA cells and covered smaller areas than the previous works. The proposed designs have been designed in a single layer without any crossover.

Ambient LoRa Backscatter System With Chirp Interval Modulation

Ambient LoRa backscatter enables battery-free wireless communication with long-range connectivity for the Internet of Things. However, current efforts mainly focus on symbol-level modulation, which trades considerable data rates for long backscatter ranges. To enhance the data rate, this paper presents and prototypes Pacim, which fully explores the potential of long-period LoRa chirps and conveys additional information by varying symbol lengths. Specifically, we propose the chirp interval modulation scheme that modulates multiple data bits in each time interval between two chirp-based anchor symbols. Moreover, we design a twin-chirp cancellation method at the receiver that eliminates the frequency discontinuity within anchor symbols, and propose a fine-grained detection algorithm to measure the arrival time of anchor symbols in the frequency domain. We further propose three reliable methods to improve transmission reliability and analyze the symbol error rate (SER) performance. We also build a hardware prototype and perform comprehensive evaluations. Our experiment results show that Pacim can achieve up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8.6 \times $ </tex-math></inline-formula> throughput gain while keeping long-range, compared with the state-of-the-art ambient LoRa backscatter design.

Index and mode modulated orthogonal frequency division multiplexing with enhanced spectral efficiency

AbstractIndex modulation aided orthogonal frequency division multiplexing (OFDM‐IM) is a potential multicarrier transmission technique for wireless data transmission systems due to its attractive error performance and energy efficiency. However, it fails to cope with increasing demand of high data rate in upcoming mobile data services, mainly, due to the lower spectral efficiency. In this communication, an efficient transmission technique, called index and mode modulation OFDM, is proposed that delivers additional information through permutations of multiple modes and indexed bits patterns resulting in higher spectral efficiency. For the proposed technique, a low complexity log‐likelihood ratio detector with suitable algorithm is designed and its computational complexity has been analysed. The simulation results indicate improved performance of this newly proposed scheme in terms of spectral efficiency, bit error rate, as well as energy efficiency over other existing index modulated and multiple mode based OFDM schemes, while maintaining considerably low computational complexity in detection. That proclaims the scheme as a potential transmission technique to meet the data transmission challenges in 5G and beyond.

A Robust Time-Based Multi-Level Sensing Circuit for Resistive Memory

Resistive random access memory (RRAM) is a promising emerging nonvolatile memory (NVM) due to its large resistance ratio in different switching states. To improve memory density and reduce cost-per-bit, multi-level cell (MLC) RRAM stores multiple bits in a single cell, compared to a single-level cell (SLC). However, random mismatch, process variation, and resistance shift lead to reliability issues, degrade the probability of correct read, and increase the bit error rate (BER). This paper presents a time-based sensing scheme for robust read operation and extends to multi-level sensing for SLC and MLC RRAM arrays. Bit line (BL) voltage is converted into time delay by a voltage-to-time converter (VTC) and compared with the implicit timing reference generated by a delay line. By detecting different states in the time domain, the proposed time-mode sense amplifier (TSA) requires no analog reference voltage or current, which is used in the conventional voltage-mode sense amplifiers (VSA) or current-mode sense amplifiers (CSA). Power gating is employed to enable the time sampling only at the sensing points to suppress the short-circuit current. A charge sharing-induced error compensation (CSEC) circuit is used to eliminate the charge sharing-induced voltage drop and expand the sense margin by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.56\times $ </tex-math></inline-formula> . Monte Carlo simulations in 40nm technology show that the proposed TSA improves read reliability and reduces BER by 3–4 orders of magnitude compared to conventional VSA and CSA. The proposed time-based sensing scheme operates from 0.7-1.2 V supply and consumes 49 fJ/bit for read operation under a nominal 1.2 V supply.

Flexible, Light-Interacting, B-Shaped Structures for Computations.

Integrating mechanical computing functions into robotic materials, microelectromechanical systems, or soft robotics can improve their intelligence in stimulation-response processes. Current mechanical computing systems exhibit limitations, including incomplete functions, unchangeable computing rules, difficulties in realizing random logic, and lack of reusability. To overcome these limitations, we propose a straightforward method of designing mechanical computing systems-based on the logic expressions-for complex computations. We designed soft, B-shaped mechanical metamaterial units, and compressed them to render stress inputs; the outputs are represented by the light-shielding effects caused by the unit deformations. We realized logic gates and corresponding combinations (including half/full binary adder/subtractor and addition/subtraction of 2 numbers with multiple bits) and provided a versatile solution for making a mechanical analog-to-digital converter to generate both ordered and disordered numbers. We performed all of the computations within the elastic regions of the B-shaped units; thus, after one computation, the systems can return to the initial states for reuse. The proposed mechanical computers will potentially enable robotic materials, microelectromechanical systems, or soft robotics to perform complex tasks. Furthermore, one can extend this concept to systems that are based on other mechanisms or materials.

A Low-Complexity Sorting Network for a Fast List Polar Decoder

Fast list decoding algorithms for polar codes have been proposed to achieve low latency and high error correction performance. In the Rate-1 and SPC nodes of fast list decoding, a high-complexity sorter is required if multiple bits are to be decoded simultaneously in a single clock cycle. This paper proposes a partitioned sorting network (PSN) that reduces the complexity of metric sorter in Rate-1 and single parity check (SPC) decoders for fast list decoding. The proposed PSN consists of two sorting networks. For the first sorting network, we analyze the order of the path metrics (PMs) and reduce the number of input candidate paths. Furthermore, for the second sorting network, we analyze the cumulative results of path selection and identify relatively frequently selected paths. The proposed PSN has up to 90% fewer compare-and-swap units (CASUs) and up to 137% higher operating frequencies than existing sorting networks for Rate-1 and SPC decoders with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L=8$ </tex-math></inline-formula> .

Hybrid Hyper Chaotic Map with LSB for Image Encryption and Decryption

There are number of images that transmitted through the web for various usages like medical imaging, satellite images, military database, broadcasting, confidential enterprise, banking, etc. Thus, it is important to protect the images confidentially by securing sensitive information from an intruder. The present research work proposes a Hybrid Hyper Chaotic Mapping that considers a3D face Mesh model for hiding the secret image. The model has a larger range of chaotic parameters which are helpful in the chaotification approaches. The proposed system provides excellent security for the secret image through the process of encryption and decryption. The encryption of the secret image is performed by using chaos encryption with hyper hybrid mapping. The hyper hybrid mapping includes enhanced logistic and henon mapping to improve the computation efficiency for security to enhance embedding capacity. In the experiment Fingerprint and satellite image is used as secret image. The secret image is encrypted using a Least Significant Bit (LSB) for embedding an image. The results obtained by the proposed method showed better enhancements in terms of SNR for the 3D Mesh model dataset as 77.85 dB better compared to the existing models that achieved Reversible data hiding in the encrypted domain (RDH-ED) of 33.89 dB and Multiple Most Significant Bit (Multi-MSB) 40 dB. Also, the results obtained by the proposed Hybrid Hyper chaotic mapping showed PSNR of 65.73 dB better when compared to the existing Permutation Substitution and Boolean Operation that obtained 21.19 dB and 21.27 dB for the Deoxyribonucleic Acid (DNA) level permutation-based logistic map.

Parallelism-Aware Channel Partition for Read/Write Interference Mitigation in Solid-State Drives

The advancement of multi-level cell technology that enables storing multiple bits in a single NAND flash memory cell has increased the density and affordability of solid-state drives (SSDs). However, increased latency asymmetry between read and write (R/W) intensifies the severity of R/W interference, so reads cannot be processed for a long time owing to the extended flash memory resource occupancy of writing. Existing flash translation layer (FTL)-level mitigation techniques can allocate flash memory resources in a balanced manner taking R/W interference into account; however, due to the inefficient utilization of parallel flash memory resources, the effect on performance enhancement is restrictive. From the perspectives of the predicted access pattern and available concurrency of flash memory resources, we propose a parallelism-aware channel partition (PACP) scheme that prevents SSD performance degradation caused by R/W interference. Moreover, an additional performance improvement is achieved by reallocating interference-vulnerable page using leveraged garbage collection (GC) migration. The evaluation results showed that compared with the existing solution, PACP reduced the average read latency by 11.6% and average write latency by 6.0%, with a negligible storage overhead.

Multi-State Memristors and Their Applications: An Overview

Memristors show great potential for being integrated into CMOS technology and provide new approaches for designing computing-in-memory (CIM) systems, brain-inspired applications, trimming circuits and other topologies for the beyond-CMOS era. A crucial characteristic of the memristor is multi-state (also often referred as multibit, and multi-level) switching. Memristors are capable of representing information in an ultra-compact fashion, by storing multiple bits per device. However, certain challenges remain in multi-state memristive circuits and systems design such as device stability and peripheral circuit complexity. In this paper, we review the state of the art of multi-state memristor technologies and their associated CMOS/Memristor circuit design, and discuss the challenges regarding device imperfection factors, modelling, peripheral circuit design and layout. We present measurement results of our in-house fabricated multi-state memristor as an example to further illustrate the feasibility of applying multi-state memristors in CMOS design, and demonstrate their related future applications such as multi-state memristive memories in machine learning, memristive neuromorphic applications, trimming and tuning circuits, etc. In the end, we summarize past and present efforts done in this field and envisage the direction of multi-state memristor related research.

Adaptive Mode Transformation for Wear Leveling in Nonvolatile FPGAs

Nowadays, field programmable gate arrays (FPGAs) have been widely adopted to serve as accelerators in artificial intelligence and big data related applications. Since the static random access memory (SRAM)-based FPGA is suffering from limited density and high leakage power, nonvolatile FPGAs have been proposed, where SRAM is replaced with emerging nonvolatile memories (NVMs). Multilevel cell (MLC), which can store multiple bits within one memory cell, further improves the density of nonvolatile FPGAs and shows great potential to enable large on-chip memory. However, it suffers from limited lifetime. In this article, we propose a wear leveling scheme to improve lifetime of MLC-based nonvolatile FPGAs. Instead of generating a series of configuration files for runtime reconfiguration, we propose to identify write-heavy MLC regions and dynamically transform them to durable single-level cell (SLC) mode. Specifically, we propose three modules: 1) pertaining to write behavior monitor; 2) approximate cost calculator; and 3) mode transformation manager to achieve adaptive mode transformations. We consider FPGA features to design these modules, which is different from implementations for MLC-SLC transformation in CPU architecture. Evaluation shows that the proposed scheme can improve lifetime for MLC nonvolatile FPGAs by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.03\times $ </tex-math></inline-formula> , at cost of 12.5% storage overhead.

Reversible Transformation between Isolated Skyrmions and Bimerons.

Skyrmions and bimerons are versatile topological spin textures that can be used as information bits for both classical and quantum computing. The transformation between isolated skyrmions and bimerons is an essential operation for computing architecture based on multiple different topological bits. Here we report the creation of isolated skyrmions and their subsequent transformation to bimerons by harnessing the electric current-induced Oersted field and temperature-induced perpendicular magnetic anisotropy variation. The transformation between skyrmions and bimerons is reversible, which is controlled by the current amplitude and scanning direction. Both skyrmions and bimerons can be created in the same system through the skyrmion-bimeron transformation and magnetization switching. Deformed skyrmion bubbles and chiral labyrinth domains are found as nontrivial intermediate transition states. Our results may provide a unique way for building advanced information-processing devices using different types of topological spin textures in the same system.

Measurement and control of a superconducting quantum processor with a fully integrated radio-frequency system on a chip.

We describe a digital microwave platform called Presto, designed for measurement and control of multiple quantum bits (qubits) and based on the third-generation radio-frequency system on a chip. Presto uses direct digital synthesis to create signals up to 9GHz on 16 synchronous output ports, while synchronously analyzing responses on 16 input ports. Presto has 16 DC-bias outputs, four inputs and four outputs for digital triggers or markers, and two continuous-wave outputs for synthesizing frequencies up to 15GHz. Scaling to a large number of qubits is enabled through deterministic synchronization of multiple Presto units. A Python application programming interface configures a firmware for synthesis and analysis of pulses, coordinated by an event sequencer. The analysis integrates template matching (matched filtering) and low-latency (184-254ns) feedback to enable a wide range of multi-qubit experiments. We demonstrate Presto's capabilities with experiments on a sample consisting of two superconducting qubits connected via a flux-tunable coupler. We show single-shot readout and active reset of a single qubit; randomized benchmarking of single-qubit gates showing 99.972% fidelity, limited by the coherence time of the qubit; and calibration of a two-qubit iSWAP gate.

Bitwise Logical Operations in VCMA-MRAM

Today’s technology demands compact, portable, fast, and energy-efficient devices. One approach to making energy-efficient devices is an in-memory computation that addresses the memory bottleneck issues of the present computing system by utilizing a spintronic device viz. magnetic tunnel junction (MTJ). Further, area and energy can be reduced through approximate computation. We present a circuit design based on the logic-in-memory computing paradigm on voltage-controlled magnetic anisotropy magnetoresistive random access memory (VCMA-MRAM). During the computation, multiple bit cells within the memory array are selected that are in parallel by activating multiple word lines. The designed circuit performs all logic operations-Read/NOT, AND/NAND, OR/NOR, and arithmetic SUM operation (1-bit approximate adder with 75% accuracy for SUM and accurate carry out) by slight modification using control signals. All the simulations have been performed at a 45 nm CMOS technology node with VCMA-MTJ compact model by using the HSPICE simulator. Simulation results show that the proposed circuit’s approximate adder consumes about 300% less energy and 2.3 times faster than its counterpart exact adder.

Fault Tolerance Method for Memory Based on Inner Product Similarity and Experimental Study on Heavy Ion Irradiation

As the feature sizes of integrated circuits are reduced to the nanometer scale, the total soft error rate (SER) in memory and the proportion of multiple bit upsets (MBUs) are significantly increasing. In order to ensure the information reliability, many error correction codes with strong error correction ability were proposed, such as Reed–Somolon (RS) code and Bose–Chaudhuri–Hocquenghem (BCH) code. However, these error correction codes have limited error correction capability, high algorithm complexity and large data redundancy. In this paper, a novel fault tolerance method for locating and correcting multiple bit errors in memory is proposed based on data similarity. The proposed method uses the inner product as the metric to analyze the similarity of the pre-protected data from the vertical and horizontal dimensions, respectively, and to construct the model of error location and correction. This method performs encoding and decoding in units of blocks and detecting and correcting in units of words, so it can correct any number of bits in a corrupted word with low redundancy overhead. Finally, irradiation tests were conducted on a commercial SRAM, and the feasibility of the proposed method is verified by using heavy ion [Formula: see text]Kr[Formula: see text] as irradiation source.

Implicit Label Number for Optical Packets in Label Switching Networks Based on Spectral Amplitude Coding and OCDM Path

This paper presents an implicit labeling scheme where stacked spectral-amplitude-coding (SAC) labels are inscribed in multiple payload bits in the packet front. Reliable label recognition in optical packet switching (OPS) is achieved by analyzing the overall decoding results of all labeled bits instead of considering each labeled signal individually. The concept of hypothesis testing is employed to determine the optimal labeled bit number. A decision rule of correct switching is designed based on the photocurrent mean of the decoded label stacks. Considering the noise factors shown in the decoding process, the desired label number has been analyzed under different conditions of code types, label power, and the level of significance. Simulation results provide good suggestions for the tradeoff between the system insensitivity to noise effects and the transmission redundancy of carrying repetitive label information in an optical packet.

High-dimensional encryption in optical fibers using spatial modes of light and machine learning

The ability to engineer the spatial wavefunction of photons has enabled a variety of quantum protocols for communication, sensing, and information processing. These protocols exploit the high dimensionality of structured light enabling the encoding of multiple bits of information in a single photon, the measurement of small physical parameters, and the achievement of unprecedented levels of security in schemes for cryptography. Unfortunately, the potential of structured light has been restrained to free-space platforms in which the spatial profile of photons is preserved. Here, we make an important step forward to using structured light for fiber optical communication. We introduce a classical encryption protocol in which the propagation of high-dimensional spatial modes in multimode fibers is used as a natural mechanism for encryption. This provides a secure communication channel for data transmission. The information encoded in spatial modes is retrieved using artificial neural networks, which are trained from the intensity distributions of experimentally detected spatial modes. Our on-fiber communication platform allows us to use single spatial modes for information encoding as well as the high-dimensional superposition modes for bit-by-bit and byte-by-byte encoding respectively. This protocol enables one to recover messages and images with almost perfect accuracy. Our classical smart protocol for high-dimensional encryption in optical fibers provides a platform that can be adapted to address increased per-photon information capacity at the quantum level, while maintaining the fidelity of information transfer. This is key for quantum technologies relying on structured fields of light, particularly those that are challenged by free-space propagation.