Multiple Bit Errors Research Articles

An analytical approach to error detection and correction for onboard nanosatellites

Nanosatellites are persistently progressing and creating global communication and data transmission. It builds up a colossal request for more progressed and dependable frameworks to transmit faster and more reliable information. A syntactic machine learning approach has been distinguished as a good plot for anticipating single-bit and multiple-bit errors that influence onboard nanosatellites. In this paper, we have proposed an analytical approach to error detection and correction for onboard nanosatellites. We have planned the framework separately with three distinct parts: encoding, error checking, and decoding. It has created an amid information exchange from satellite to the ground station. It has analyzed six camera pictures simultaneously with the assistance of field programmable gate array and EDAC strategies. We have presented the progressed turbo mechanics EDAC for unprecedented transfer speeds of satellite communication and execution & examination with the AWGN and Rayleigh channels to extend the proficiency. EDAC strategies codes have been implemented in MATLAB. This method is straightforward and accomplishes unwavering quality and exactness compared to comparable strategies.

Configuration Memory Scrubbing of SRAM-Based FPGAs Using a Mixed 2-D Coding Technique

SRAM-based field-programmable gate array (FPGA) vendors typically integrate error correction codes (ECCs) into the configuration memory to assist designers in implementing scrubbing mechanisms. In most cases, these ECC schemes guarantee the correction of single- and double-bit errors per configuration frame but fail to correct upsets with higher multiplicity in a single frame caused by a single event. This phenomenon has been observed in modern commercial-off-the-shelf FPGAs. Bit interleaving schemes are used in some FPGA families to scatter the multiple upsets into more than one frame, but this does not fully resolve the problem of uncorrectable errors. In this article, we propose a configuration memory scrubbing approach for SRAM-based FPGA devices, which combines the embedded ECC logic with an interframe, interleaved parity code to build a mixed 2-D coding technique. The proposed technique improves the multiple-bit error correction capabilities of the on-chip ECC scheme while keeping the error correction latency and hardware cost low. The scrubbing concept has been validated under heavy-ion irradiation, where it succeeded in correcting all the single and multiple upsets observed during the radiation experiment.

A Write-Buffer Scheme to Protect Cache Memories Against Multiple-Bit Errors

A Write-Buffer Scheme to Protect Cache Memories Against Multiple-Bit Errors

An Empirical Study of the Impact of Single and Multiple Bit-Flip Errors in Programs

Recent studies have shown that technology and voltage scaling are expected to increase the likelihood that particle-induced soft errors manifest as multiple-bit errors. This raises concerns about the validity of using single bit-flips in fault injection experiments aiming to assess the program-level impact of soft errors. The goal of this article is to investigate whether multiple-bit errors could cause a higher percentage of silent data corruptions (SDCs) compared to single-bit errors. Based on 2700 fault injection campaigns with 15 benchmark programs, featuring a total of 27 million experiments, our results show that single-bit errors in most cases either yield a higher percentage of SDCs compared to multiple-bit errors or yield SDC results that are very close to the ones obtained for the multiple-bit errors. Further, we find that only around 2 percent of the multiple-bit campaigns resulted in an SDC percentage that was more than 5 percentage points higher than that obtained for the corresponding single-bit campaigns. For most of these campaigns, the highest percentage of SDCs was obtained by flipping at most 3 bits. Based on our results, we also propose four techniques for error space pruning to avoid injection of multiple-bit errors that are either unlikely or infeasible to cause SDCs.

An Error Location and Correction Method for Memory Based on Data Similarity Analysis

The nanoscale CMOS technology has encountered severe reliability issues, especially in the on-chip memory. As the technology nodes keep shrinking, single-event upsets (SEUs) may encounter more frequent multiple-bit upsets (MBUs) per particle strike. The commonly used memory error correction methods, such as the single-error correction–double-error detection (SEC–DED) code, are no longer feasible. While the counterparts for multiple error correction codes (MECs) yield too costly overhead on delay and data redundancy, especially for MBUs in a word or a character, even with all bits upset, the error correcting ability of the existing error correcting methods is exceeded. In this paper, we introduce a novel block-based error detection and correction method for memory by analyzing the similarity of data. This method of error location and correction can cope with both single-word error (SWE) and multiple-word error (MWE), no matter how many corrupted bits of each word there are. Experimental results on the test system based on SRAM demonstrate that the proposed method can correct single-word–single-bit (SWSB), single-word–multiple-bit (SWMB), multiple-word–single-bit (MWSB), and multiple-word–multiple-bit (MWMB) errors. The proposed method based on block level greatly improved the correction ability with low redundancy, low decoding delay, and moderate complexity versus other homogeneous byte-level or bit-level protection methods. In particular, the detection and correction efficiency is more evident when the data size increases.

Synthesis of a Concurrent Error Detection Circuit Based on the Spectral R-Code with the Partitioning of Outputs into Groups

The pace of development of the microelectronic industry and the progress in the development of computer-aided design tools make problems associated with the development of combinational circuits that are resistant to short self-clearing faults relevant again. These faults occur due to a combination of many different factors, such as extreme operating conditions and transition to nanometer design standards. Structural redundancy methods are often used to solve this problem by the principles of the noiseless coding theory to protect information during its transmission over communication channels. However, these methods have a significant drawback, i.e., large structural redundancy. In this paper, we propose to use an approach based on the synthesis of fault-tolerant combinational circuits based on the spectral R-code to solve the problem of developing fault tolerant combinational circuits. If a specific part of the coder is protected using special technological means, this code can correct a single-bit error and detect a double-bit error. The resulting circuit has less structural redundancy compared to the traditional method of triple modular redundancy (TMR). An approach is also proposed based on partitioning circuit outputs into groups followed by synthesizing fault-tolerant combinational circuits based on the R-code, which increases the probability of error detection/correction, to minimize the probability of multiple-bit errors within a combinational circuit. The paper presents the results of a series of numerical experiments that show the efficiency of the proposed approaches.

RAW-Tag: Replicating in Altered Cache Ways for Correcting Multiple-Bit Errors in Tag Array

Tag array in on-chip caches is one of the most vulnerable components to radiation-induced soft errors. Protecting the tag array in some processors is limited to error detection using the parity check, since the overheads of error correcting codes are not affordable in this component. State-of-the-art tag protection schemes combine the parity check with replication to provide error correction capability. Classifying these replication-based schemes into partial-replication and full-replication, the former offers a low overhead protection in which a large fraction of detectable errors remain uncorrectable, whereas the latter imposes a significant overhead to correct all of the errors. This paper proposes a low overhead full-replication scheme, so called Replicating in Altered Ways of Tag (RAW-Tag), to correct all detectable errors. RAW-Tag manipulates the cache replacement algorithm and keeps track of the incoming/evicting cache lines to not only provide a replica for all tags, but also eliminate the simultaneous susceptibility of both a tag and its replica to a single Multiple-Bit Upset (MBU). The simulation results show that RAW-Tag imposes no performance overhead and increases the energy consumption of L1 and L2 caches by only 6.6 and 0.3 percent, respectively, as compared with the baseline.

Implementation and evaluation of 2D SEC-DED forward error correction scheme in wireless sensor networks

Numerous applications in wireless sensor networks (WSNs) require collecting data without loss during transmission, long-term sensing, and long system lifetime. Achieving reliable data transfer and long system lifetime is difficult because, from one hand, the wireless transfer is error prone, and, on the other, sensor node (SN), as battery powered device, is energy limited. By using some power-aware techniques, such as duty-cycling and power-gating, it is possible to reduce the energy consumption at an acceptable level. The requirements for higher level of reliability during wireless data transfer have increased the use of error correcting codes (ECCs). Codes represent an effective means of providing protection against injection of single-/double-/multiple bit errors over noisy communication channel. The two basic mechanisms to recover erroneous packets in any network are Automatic Repeat Request (ARQ), and Forward Error Correction (FEC). As energy consumption is a major issue in concern in WSN, packet retransmission is not an option and FEC would be preferred over ARQ. In this paper, an efficient scheme, based on two-dimensional (rectangular) block ECC code, referred as Two Dimensional Single Error Correction and Double Error Detection (2D SEC-DED), has been developed. By using 2D SEC-DED encoding all single-bit and 99.9% of double−/multiple-bit errors, within transferred packets, are recovered. In this way, the number of retransmissions, when WSN operates in harsh environmental (bit error rate (BER), BER>10−4) is decreased, what means that not only energy saving but also extension of the transmit range (transmission distance between the transmitter and receiver), is achieved. As illustration, for indoor environment (the path loss exponent, also known as propagation constant or space loss factor, α=4) at the target BER of 5·10−4, the proposed encoding scheme is able to improve the transmission distance by about 18m or the received signal strength (RSSI) by about 8.5dBm compared to WSN without error correction (WSN which use Cycle Redundancy Check (CRC) encoding as error detection mechanism).

A 0.35 V, 375 kHz, 5.43 µW, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line

This paper presents a disturb-free 10T subthreshold SRAM cell with fully-symmetrical structure and tri-state pre-charge free bit-line (BL). The disturb-free feature facilitates bit-interleaving architecture that can reduce multiple-bit errors in a single word and enhance soft error immunity by employing error checking and correction (ECC) techniques. The fully-symmetrical cell structure provides balanced margin and performance in advanced strained-silicon and/or FinFET technologies where PMOS strength approaches that of NMOS. The tri-state BL is left floating in standby state to minimize switching activity for energy efficiency. The scheme eliminates the need of BL keeper, provides balanced two-transistor stack read for better read performance, and eases the design and migration. The proposed 10T SRAM cell is demonstrated by 128kb SRAM macro implemented in 40nm low-power (40LP) CMOS technology. Measured read and write functionality is demonstrated with VDD down to 0.35V (~100mV lower than the threshold voltage). Data is held down to 0.325V with 2.53µW standby power. The measured maximum operation frequency is 375kHz with total power consumption 5.43µW at 0.35V.

40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist

This paper presents a new bit-interleaving 12T subthreshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to improve the Write-ability to mitigate increased device variations at low supply voltage under deep sub-100 nm processes. The disturb-free feature facilitates the bit-interleaving architecture that can reduce multiple-bit errors in a single word and enhance soft error immunity by employing error checking and correction (ECC) techniques. The proposed 12T SRAM cell is demonstrated by a 4 kb SRAM macro implemented in 40 nm general purpose (40GP) CMOS technology. The test chip operates from typical VDD to 350 mV ( ~ 100 mV lower than the threshold voltage) with VDDMIN limited by Read operation. Data can be written successfully for VDD down to 300 mV. The measured maximum operation frequency is 11.5 MHz with total power consumption of 22 μW at 350 mV, 25 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C.

A Single-Bit and Double-Adjacent Error Correcting Parallel Decoder for Multiple-Bit Error Correcting BCH Codes

This paper presents a novel high-speed BCH decoder that corrects double-adjacent and single-bit errors in parallel and serially corrects multiple-bit errors other than double-adjacent errors. Its operation is based on extending an existing parallel BCH decoder that can only correct single-bit errors and serially corrects double-adjacent errors at low speed. The proposed decoder is constructed by a novel design and is suitable for nanoscale memory systems, in which multiple-bit errors occur at a probability comparable to single-bit errors and double-adjacent errors occur at a higher probability (nearly two orders of magnitude) than other multiple-bit errors. Extensive simulation results are reported. Compared with the existing scheme, the area and delay time of the proposed decoder are on average 11% and 6% higher, but its power consumption is reduced by 9% on average. This paper also shows that the area, delay, and power overheads incurred by the proposed scheme are significantly lower than traditional fully parallelized BCH decoders capable of correcting any double-bit errors in parallel.

Reliable Concurrent Error Detection Architectures for Extended Euclidean-Based Division Over &lt;inline-formula&gt; &lt;tex-math notation="TeX"&gt;${\rm GF}(2^{m})$ &lt;/tex-math&gt;&lt;/inline-formula&gt;

The extended Euclidean algorithm (EEA) is an important scheme for performing the division operation in finite fields. Many sensitive and security-constrained applications such as those using the elliptic curve cryptography for establishing key agreement schemes, augmented encryption approaches, and digital signature algorithms utilize this operation in their structures. Although much study is performed to realize the EEA in hardware efficiently, research on its reliable implementations needs to be done to achieve fault-immune reliable structures. In this regard, this paper presents a new concurrent error detection (CED) scheme to provide reliability for the aforementioned sensitive and constrained applications. Our proposed CED architecture is a step forward toward more reliable architectures for the EEA algorithm architectures. Through simulations and based on the number of parity bits used, the error detection capability of our CED architecture is derived to be 100% for single-bit errors and close to 99% for the experimented multiple-bit errors. In addition, we present the performance degradations of the proposed approach, leading to low-cost and reliable EEA architectures. The proposed reliable architectures are also suitable for constrained and fault-sensitive embedded applications utilizing the EEA hardware implementations.

Single Event Induced Multiple Bit Errors and the Effects of Logic Masking

We apply a model and heavy-ion cross section data to predict the potential that one single event upset (SEU) will induce multiple bit errors (MBEs) by the next clock-cycle of a synchronous design.

A 10T Cell Design without Half Select Problem for Bit-Interleaving Architecture in 65nm CMOS

With the scaling of process technologies into the nanometer regime, multiple-bit soft error problem becomes more serious. In order to improve the reliability and yield of SRAM, bit-interleaving architecture which integrated with error correction codes (ECC) is commonly used. However, this leads to the half select problem, which involves two aspects: the half select disturb and the additional power caused by half-selected cells. In this paper, we propose a new 10T cell to allow the bit-interleaving array while completely eliminating the half select problem, thus allowing low-power and low-voltage operation. In addition, the RSNM and WM of our proposed 10T cell are improved by 21% and nearly one times, respectively, as compared to the conventional 6T SRAM cell in SMIC 65nm CMOS technology. We also conduct a comparison with the conventional 6T cell about the leakage simulation results, which show 14% of leakage saving in the proposed 10T cell.

Soft error recovery in simplex and triplex memory systems

This paper analyzes and compares the reliability and MTTF of four fault-tolerant memory configurations subject to soft errors, namely (i) the SEC protected RAM (SEC-RAM), (ii) the SEC-unprotected triplex RAM (TMR-RAM), (iii) the triplex SEC-protected RAM (TMR-SEC RAM) and (iv) the SEC-protected triplex RAM (SEC-TMR RAM). The last two configurations are new and their difference lies on the order of performing the voting and decoding operations. Depending on the configuration, memory modeling is accomplished by Markov models either at the bit or at the word level, by also taking into account the canceling of soft errors due to subsequent soft errors. Exact theoretical expressions for the reliability and MTTF of the SEC-RAM and TMR-RAM are developed and two alternative recursive algorithms are given to assess the impact of memory scrubbing on MTTF. The advantage of both the proposed configurations is that they can tolerate all possible error patterns with three errors and they also present a remarkable resistance to error patterns with a much larger number of errors. As the analysis of the SEC-TMR RAM cannot be accomplished theoretically, due to the varying error-patterns of the SEC decoder output for more than one error in a codeword, a fast error-pattern generation algorithm (FEP) is developed. Simulation results show that there exist numerous multiple-bit error patterns in more than two words in the SEC-TMR RAM that upon decoding and voting produce the correct data-word. A comparison of the multiple-bit error masking capability of the TMR-SEC and SEC-TMR is also given.

On Concurrent Detection of Errors in Polynomial Basis Multiplication

The detection of errors in arithmetic operations is an important issue. This paper discusses the detection of multiple-bit errors due to faults in bit-serial and bit-parallel polynomial basis (PB) multipliers over binary extension fields. Our approach is based on multiple parity bits. Experimental results presented here show that due to an increase in the number of parity bits, the area overhead tends to increase linearly, but the probability of error detection approaches unity fairly quickly, e.g., for eight parity bits. In bit-serial implementation of a GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">163</sup> ) PB multiplier using eight parity bits, the area overhead and the probability of error detection are 10.29% and 0.996, respectively. This is achieved without any increase in the computation time of the GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">163</sup> ) PB multiplier

A software tool for fault tolerance

This paper describes a software fix in order to tolerate multiple transient-faults in an application using code-redundancy of an application program that is enhanced with a new error-checking and switching technique. It is a low cost solution towards tolerating multiple bit-errors. This technique which is based on enhanced single-version scheme (ESVS), does not intend to correct errors. Rather it aims to mask various operational and environmental errors during the run-time of an application.

On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check

This paper proposes the Cross-Parity check as a method for an on-line detection of multiple bit-errors in registers or register files of microprocessors. Transient or ‘soft’ errors caused by radiation as single event upsets (SEUs) or electromagnetic coupling are in the focus of this work. Especially for register files or register groups, an easy implementable error correction method is proposed, which can be implemented by software routines or additional hardware. The method is based on the logical interpretation of Cross-Parity vectors.

Serendipitous SEU hardening of resistive load SRAMs

High and low resistive load versions of Micron Technology's MT5C1008C (128K/spl times/8) and MT5C2561C (256K/spl times/1) SRAMs were tested for SEU vulnerability. Contrary to computer simulation results, SEU susceptibility decreased with increasing resistive load. A substantially larger number of multiple-bit errors was observed for the low resistive load SRAMs, which also exhibited a "1"/spl rarr/"0" to "0"/spl rarr/"1" bit error ratio close to unity; in contrast, the high resistive load devices displayed a pronounced error bit polarity effect. Two distinct upset mechanisms are proposed to account for these observations.

SEE results using high energy ions

SEE data on SRAMs and DRAMs, obtained with low and high energy ions, are presented. The global response of these devices remained coherent using low or high energy beams (angle effects, pattern influences, multiple-bit error proportion, etc.), but discrepancies appeared, in some cases, in the threshold part of the sensitivity curves. These anomalies seem in relation with a track structure.