Multimicroprocessor Systems Research Articles

INTELLIGENT SOLVING MACHINES ON MODERN PARALLEL ARCHITECTURES

The paper considers the creation of intelligent solving machines and the arrangement of parallel programming in intelligent distributed multiprocessor systems based on them. There are proposed some main concepts. A system is designed for programming in the C+Graph high-level language. The ideology proposed can be considered as an efficient development of structural high-level language interpretation when applied to multi-microprocessor systems. Equipment structure of the basic version of intelligent solving machines is considered and some characteristics are discussed.

Scheduling multiprocessor tasks with chain constraints

This paper is concerned with a new model in deterministic scheduling theory, where certain tasks may require more than one processor at a time. This model is motivated by several applications of multimicroprocessor systems and it has received much attention in the last years. In the paper it is assumed that each task can be processed on any processor subset of a given task-dependent size. Tasks are nonpreemptable and there are precedence constraints among them. It is proved that the problem of minimizing schedule length is NP-hard for three processors even if all the tasks have unit processing times and precedence constraints form a set of chains. Thus, it is unlikely to be solvable in polynomial time. On the other hand, two low order polynomial-time algorithms are given for the m processor case if processor requirements of the tasks in each chain are either uniform or monotonically decreasing (increasing).

MP: an application specific concurrent language

In this paper we present the defininition, and implementation of a concurrent language mp (Message Passer), which is aimed at programming embedded multi micro-processor systems. The novel features of the language includes the ability to program and develop the entire distributed system as a single unit, and the provision of simple restricted concurrency constructs that make such systems modular and deadlock free. mp programs are invariant with respect to the characteristics of a particular target machine, for instance, the number of processors, and their mutual connectivity. Programs written in mp can be transformed to a restricted set of Communicating Sequential Processes (CSP), in which particular specifications can be shown to be satisfied. The restricted model of concurrency, does not prevent the language being able to express all of the known course grained parallel programming paradigms. However, the structured nature of the code makes the model particularly attractive in concurrent embedded systems, where deadlock freedom and program correctness are prime issues. An mp program is a collection of objects which execute concurrently, maintain their own local state and connect with other objects via bound variables. Explicit communication between objects is totally transparent to the application programmer. A compiler for the language has been built and a multiprocessor run time environment has been established for any system with a C compiler and the message passing standard MPI library. Several applications have been tested, ranging from a clocked digital circuit simulation, to a simple event driven process controller.

MP: an application specific concurrent language

In the paper the authors present the defininition and implementation of a concurrent language MP (message passer) which is aimed at programming embedded multi-microprocessor systems. The novel features of the language include the ability to program and develop the entire distributed system as a single unit, and the provision of simple restricted concurrency constructs that make such systems modular and deadlock free. MP programs are invariant with respect to the characteristics of a particular target machine, for instance, the number of processors, and their mutual connectivity. Programs written in MP can be transformed to a restricted set of communicating sequential processes (CSP), in which particular specifications can be shown to be satisfied. The restricted model of concurrency does not prevent the language being able to express all of the known course-grained parallel programming paradigms. However, the structured nature of the code makes the model particularly attractive in concurrent embedded systems, where deadlock freedom and program correctness are prime issues. An MP program is a collection of objects which execute concurrently, maintain their own local state and connect with other objects via bound variables. Explicit communication between objects is totally transparent to the application programmer. A compiler for the language has been built and a multiprocessor run-time environment has been established for any system with a C compiler and the message-passing standard MPI library. Several applications have been tested, ranging from a clocked digital circuit simulation, to a simple event-driven process controller.

Neural growing networks as a model of an intelligent multimicroprocessor system with a neuron-ensemble structure

This paper considers some issues of construction of intelligent multimicroprocessor systems on the basis of neural growing networks.

Multiprocessor task scheduling with resource requirements

One of the most important problems arising in multiprocessor systems is scheduling of tasks on a set of parallel processors. Recently, new models of task processing have been formulated in which certain tasks can require more than one processor at a time. This model is especially justified in some applications of multi-microprocessor systems. In this paper, we extend the above model to cover the case of scheduling in the presence of additional scarce resources. First a subcase of the problem is considered in which preemptable tasks need simultaneously one or two processors and one additional resource in the amount of one unit. For this case a low order polynomial-time algorithm is presented. Then the general case is solved via a linear programming approach.

Cubical multiprocessor architecture for solving partial differential equations in three dimensions

A cubical architecture is proposed for multi-microprocessor systems for solving partial differential equations in three dimensions, for possible use in weather forecasting and other similar applications. The architecture makes use of hundreds of processing elements to increase throughput. The system can achieve high performance and does not suffer greatly from interproccssor propagation delay.

Adaptive-intelligent control of robots and technological equipment of intelligent manufacturing

Methods of adaptive-intelligent control of robots and technological equipment of intelligent manufacturing (IM) with incomplete information on the plant conditions are discussed. Flexible algorithms are proposed for programming and sensor correction of movements which provide adaption to obstacles and uncertainly factors. Robust and adaptive control algorithms which compensate the uncontrollable disturbances and ensure the wanted character of transient process are synthesized. The conversational means and computeraided design technology for multi-microprocessor adaptive control systems of robots and technological equipment are described. The results of using the proposed methods in adaptive-intelligent control systems of robots and flexible manufacturing systems (FMS) for powder metallurgy, laser processing are presented.

Design of a second-level cache chip for shared-bus multimicroprocessor systems

The design of a second-level cache chip with the most suitable architecture for shared-bus multiprocessing is described. This chip supports high-speed (160-MB/s) burst transfer between multilevel caches and a newly proposed cache-consistency protocol. The chip, which supports a 50-MHz CPU and uses 0.8 mu m CMOS technology, includes a 32 kB data memory, 42 kb tag memory. and 21.7 K-gate logic. >

Composition of Multiple D.O.F. Robot Control System Using a Parallel Processing Microcomputer

In this paper, a method of composition for a multimicroprocessor robotic systems and a concrete example of a mobile anthropomorphic manipulator are discussed. There are many methods to compose multimicroprocessor systems for robots and complex mechatronic units. It is most advantageous for multiple degrees of freedom robots to introduce a concurrent system employing microcomputers designed on the premise of parallel connection, as it is easy to realize high speed and efficiency. In addition, hardware and software design as well as related debugging is very easy. A mobile anthropomorphic manipulator (WAM-9) with 7 d.o.f. in the arm, 16 d.o.f. in the hand and 3 d.o.f. in the body has been developed aimed at improving the robot dexterity. The control system of WAM-9 employs a 32-bit ""Transputer"" parallel processing microcomputer. This system includes about 20 transputers and is modeled after the human central nervous system.

Parallel processing of robot arm dynamic control computation on multimicroprocessors

The paper reviews research on parallel processing of robot arm control computation, which has attracted much attention to develop a cost-effective, compact and advanced controller that allows the robot system to perform complicated operations quickly and accurately in various environments, such as in space or on the ocean floor. Many parallel processing hardware and software schemes have been proposed, especially for dynamic control computation, which allow a robot arm to trace a desirable path quickly and accurately. Among this research, that relating to multimicroprocessor systems, and which will soon be put to practical use, is described in this paper. Several parallel processing schemes for a robot arm dynamics computation based on the Newton-Euler equations, which is known to be the most efficient algorithm, are detailed.

A new DMA method for single- and multimicroprocessor systems

The authors present a new DMA system where the CPU need not be kept inactive during the clock cycles where the direct memory access is performed. The method is especially interesting because it allows simultaneous data processing and transmission and in particular to the signal processing from integrated sensor systems (ISS). The procedure is based on the sharing of the RAM memory by the CPU and the DMA controller, so both of them can read or write in memory during the same clock cycle without conflict. This simple but powerful method is easily compatible with a multimicroprocessor system based on a shared memory structure.

Algorithmic programming language for multimicroprocessor systems with bus architecture

Algorithmic programming language for multimicroprocessor systems with bus architecture

On a Discrete Time Adaptive Control System with Multiple Models and its Selecting Functions

A discrete time adaptive control methodology using multiple models representing a real system in different operating conditions is presented. In the proposed method, the real plant is identified simultaneously by several models with different structure and an adoptive control is carried out using a controller designed by a certain model selected by some rules. The selection rules of the suitable model for an operating condition are decided by theoretical and experiential knowledge about the parameter estimation and adaptive control. This method requires few a priori information about the controlled plant. Moreover, this method can be applied for stable or unstable, and minimum phase or non-minimum phase plants with variable characteristics depending the operating conditions. From the practical point of view, this control algorithm is characterized by a parallel structure, and it can easily implemented by multi microprocessor systems.

Automatic unit delay execution circuit for digital signal processing systems based on general-purpose microprocessors

A simple circuit is proposed for automatic unit delay execution during the implementation of digital filters on general purpose microprocessors. The hardware overhead of the circuit is negligible, independent of the filter order and of the number of microprocessors (in the case of multimicroprocessor systems). The software overhead is zero. >

FIFTH on the transputer

FIFTH, a recently introduced, simple, stack oriented language for programming multimicroprocessor systems, has been implemented on the Transputer, the new 32-bit RISC processor from INMOS for multiprocessor applications. This article presents some of the technical aspects of the implementation. Moreover, the reader will find a description of the general procedure of how to extend the FIFTH programming system to a new processor, some general remarks on implementing stack oriented languages on microprocessors and code optimisation, and a discussion of the FIFTH communication model in comparison to the Occam model implemented in the Transputer hardware.

REYSM, a high performance, low power multi-processor bus

In order to build lower cost multimicroprocessor systems, a narrow synchronous bus (15 active lines) is proposed. It multiplexes address and data on 8 bits, and arbitrates in two pipe-lined cycles on four lines. Due to the 20 to 40 MHz bus clock, and the pipelined control logic, the performances are equivalent to Multibus-2, IEEE-P896 and similar 32-bit buses. For the implementation, cards are disposed radially around a special connector. The very short connections allows for the usage of fast HC-MOS drivers with only a light adaptation.

Performance analysis of common bus multimicroprocessor systems

Performance analysis of a common bus multimicroprocessor system is given, utilizing bus interference and speedup as measures. Three mathematical models are developed, one a discrete time queueing model, the second a Markov model, and the third an approximate-probability model. Comparison of results obtained with hardware measurements and a computer simulation help calibrate these mathematical models.

Message-passing primitives for multimicroprocessor systems

Concurrent and distributed processing systems based on multiple microprocessors are both feasible and desirable. Processes residing on different processors execute in parallel while processes allocated on the same processor execute in a multiprogramming environment. These processes normally have to communicate and synchronize in order to achieve a common goal. Communication and synchronization are usually achieved by calling primitives supplied by a kernel. The paper describes a model of implementation for message-passing primitives which must be added to a single-processor kernel for communication and synchronization purposes in multimicroprocessor systems.

Switched memory for multiprocessor MC6809E systems

An increasing interest is being shown in the use of multimicroprocessor systems in a variety of applications. It is often desirable that the constituent processors have a fast communications link for the sharing of data and/or results. Both of these aims can be achieved by the sharing of blocks of memory between the two or more processors; this method has the added advantage of little, or in some cases no, software overhead. The design of a shared memory system for Motorola MC6809E microprocessors is presented.