Multilevel Metallization Research Articles

Research and Implementation on Critical Technology of Chemical Mechanical Polishing Tool for 300 mm Wafer

As the feature size scales down and the implementation of multilevel metallization, chemical mechanical polishing(CMP) has become one of the most important technologies in the ultra-large-scale integrated circuits manufacturing. However, the 300 mm wafer CMP tool is being increasingly monopolized by only a few foreign companies, and therefore the research level of 300 mm wafer CMP in our country is far behind other countries such as U.S., Japan, and South Korea. The critical technology of the 300 mm wafer CMP tool is studied. Firstly a 300 mm wafer multi-zone polishing head with pressure control system is developed, vacuum chuck and floating retainer ring are also available in the polishing head. And then the static and dynamic performance of the closed-loop pressure control system is tested. Finally a 300 mm wafer CMP tool is developed, and the 300 mm wafer CMP process flow is developed, improved, and optimized, which establishes the foundation for experimental research. The experimental results show that a material removal rate of 671.3 nm/min, and a within wafer non-uniformity of 3.93 % can be realized by the developed 300 mm wafer CMP tool.

Radiation Effects in SiGe Technology

Silicon-Germanium (SiGe) technology effectively merges the desirable attributes of conventional silicon-based CMOS manufacturing (high integration levels, at high yield and low cost) with the extreme levels of transistor performance attainable in classical III-V heterojunction bipolar transistors (HBTs). SiGe technology joins together on-die high-speed bandgap-engineered SiGe HBTs with conventional Si CMOS to form SiGe BiCMOS technology, including all the requisite RF passive elements and multi-level thick-Al metalization required for high-speed circuit design. Such an silicon-based integrated circuit technology platform presents designers with an ideal division of labor for realizing optimal solutions to many performance-constrained mixed-signal (analog + digital + RF) systems. The unique bandgap-engineered features of SiGe HBTs enable several key merits with respect to operation across a wide variety of so-called “extreme environments”, potentially with little or no process modification, ultimately providing compelling advantages at the circuit and system level, across a wide class of envisioned commercial and defense applications. Here we give an overview of this interesting field, focusing primarily on the intersection of SiGe HBTs, and circuits built from them, with radiation-intense environments such as space.

Peculiarities of measurements in scanning electrical-conductivity microscopy

Functional capabilities of the scanning electrical-conductivity microscopy (SECM) in determining the electrical conductivity of nano-sized elements, studying the nanostructure of conductive coating materials, and evaluating the conductivity of nano-objects are described. The applicability of the SECM to finding imperfections in the multilevel metallization of integrated circuits with a nano-sized topology is demonstrated.

Impact of Pad Conditioning on Thickness Profile Control in Chemical Mechanical Planarization

Chemical mechanical planarization (CMP) has been proven to be the best method to achieve within-wafer and within-die uniformity for multilevel metallization. Decreasing device dimensions and increasing wafer sizes continuously demand better planarization, which necessitates better understanding of all the variables of the CMP process. A recently highlighted critical factor, pad conditioning, affects the pad surface profile and consequently the wafer profile; in addition, it reduces defects by refreshing the pad surface during polishing. This work demonstrates the changes in the postpolish wafer profile as a function of pad wear. It also introduces a wafer material removal rate profile model based on the locally relevant Preston equation by estimating the pad thickness profile as a function of polishing time. The result is a dynamic predictor of how the wafer removal rate profile shifts as the pad ages. The model helps fine-tune the pad conditioner operating characteristics without the requirement for costly and lengthy experiments. The accuracy of the model is demonstrated by experiments as well as data from a real production line. Both experimental data and simulations indicate that the smaller conditioning disk size and extended conditioning sweep range help improve the post-CMP wafer planarization. However, the defectivity tends to increase when the conditioning disk sweeps out of the pad radius; hence, the pad conditioning needs to be designed by considering the specific requirements of the CMP process conducted. The presented model predicts the process outcomes without requiring detailed experimentation.

Low-Shrinkage Spin-On Glass for Low Parasitic Capacitance Gap-Filling Process in Advanced Memory Devices

A new low-dielectric-constant spin-on glass (SOG) with a k value of 2.4 has been developed for a gap-filling process in advanced memory devices. The low-shrinkage characteristic of the SOG during thermal curing provides capabilities of gap filling and planarizing as high as those of conventional reflowable SOGs. The low-shrinkage SOG has thermal stability up to 800 °C and chemical stability against diluted hydrofluoric acid, sulfuric acid–hydrogen peroxide, and amine-based solutions, which makes it possible to be used as an interlevel dielectric of memory devices. Tungsten and aluminum interconnects fabricated using the low-shrinkage SOG showed a parasitic capacitance 30% lower than those fabricated using silicon dioxide and a sufficiently long line-to-line dielectric breakdown lifetime. Taking advantage of the high chemical stability of the SOG, an all-wet damageless via-formation process using an amine-based photoresist stripper has been developed. By using the process, the low-shrinkage SOG can be applied to multilevel metallization.

Advanced Slurry Formulations for New Generation Chemical Mechanical Planarization (CMP) Applications

ABSTRACTChemical Mechanical Planarization (CMP) is widely used to ensure planarity of metal and dielectric surfaces to enable photolithography and hence multilevel metallization in microelectronics manufacturing. The aim of this study is to establish a fundamental understanding on the dynamic growth of nano-scale protective oxide thin films during CMP to enable the selection of proper oxidizer concentrations for slurry formulations. Tungsten was selected as the model metal film to study the formation of these metal oxide films in various oxidizers and Atomic Force Microscope (AFM) was used to measure the surface roughness of the samples conditioned in the oxidizer environment before and after the CMP was conducted. The affect of surface roughness on wettability of the surfaces were also studied through contact angle measurements on the treated tungsten films. Fourier Transform Infrared Spectroscopy with Attenuated Total Reflectance FTIR/ATR technique in combination with the X-Ray Reflectivity (XRR) were utilized to determine the thicknesses of the oxidized nano films on the tungsten surface. The results were evaluated through the material removal responses reported in the literature for the W-CMP in addition to the comparison of the Pilling-Bedworth ratios of the oxidized nano films to determine the ability of the created oxide film as a self-protective oxide.

Influence of air gaps on the thermal–electrical–mechanical behavior of a copper metallization

Shrinking the IC dimensions the dielectric insulation between metal interconnects has become one of the major limits on increasing circuit speed. A lot of possible new low-k materials failed to meet specifications: too leaky, too soft, too unstable, and too expensive. Due to this air gaps beside the metallization are one solution. The reliability of ULSI multilevel copper metallizations under electro- and stress migration stress test conditions is investigated here with finite element analysis. A determination of the electrical and mechanical stress in a 3D copper metallization model based on the 45nm technology node is carried out and the impact of a variation of the applied current density as well as geometrical parameters on the thermal–electrical and mechanical behavior is investigated. For a determination of the reliability the mass flux and mass flux divergence are separately calculated by a user routine. The influence of air gaps on single via structures and structures with a chain of four vias on the thermal–electrical–mechanical behavior is determined.

Investigation of cleaning solution composed of citric acid and 5-aminotetrazole

In a damascene process for a copper metallization, the planarization method based on a chemical mechanical polishing (CMP) has been used for multilevel metallization. Although a buffing step was adopted in this CMP process, numerous residual abrasives, capable of increasing the resistance of copper lines, still existed after the second CMP step. For this reason, more research has focused on identification of an effective cleaning solution. We investigated a new cleaning solution consisting of citric acid and 5-aminotetrazole (ATRA) as a complexing agent and corrosion inhibitor, respectively. The citric acid was added to achieve a lift-off effect by removing the underlying copper oxide layer, whereas the ATRA was adopted to prevent abrasive re-adsorption by forming a passivation layer on the copper surface. The cleaning solution consisting of 0.006 M citric acid and 0.006 M ATRA displayed a particle density of 0.07 #/μm2 in an immersion test, and no particles were observed on a 4 cm2 coupon wafer in a real process test at pH 12.

Elastically Stretchable Insulation and Bilevel Metallization and Its Application in a Stretchable RLC Circuit

Stretchable electronics need stretchable wiring membranes that are equivalent to printed wiring boards but with elastically stretchable insulators and multilevel metallization. We have developed technology for elastically stretchable two-level metallization on an elastomeric membrane. Two levels of conductors were separated by a photopatternable elastomeric dielectric and connected through via holes. They were evaluated at uniaxial tensile strains of up to 30% and then used to create an elastomeric resistor–inductor–capacitor (RLC) circuit, whose alternating-current (AC) response was measured at biaxial tensile strains of up to 6%. We describe the fabrication process, morphology, and electrical performance of the bilevel metallization and the RLC circuit.

Development of spin-on-glass process for triple metal interconnects

Spin-on-glass (SOG), an interlayer dielectric material applied in liquid form to fill narrow gaps in the sub-dielectric surface and thus conducive to planarization, is an alternative to silicon dioxide (SiO2) deposited using PECVD processes. However, its inability to adhere to metal and problems such as cracking prevent the easy application of SOG technology to provide an interlayer dielectric in multilevel metal interconnect circuits, particularly in university processing labs. This paper will show that a thin layer of CVD SiO2 and a curing temperature below the sintering temperature of the metal interconnect layer will promote adhesion, reduce gaps, and prevent cracking. Electron scanning microscope analysis has been used to demonstrate the success of the improved technique. This optimized process has been used in batches of double-poly, triple-metal CMOS wafer fabrication to date.

Ragtime (review)

Reviewed by: Ragtime Mary Jo Lodge Ragtime. Book by Terrence McNally, based on the novel by E. L. Doctorow. Music by Stephen Flaherty. Lyrics by Lynn Ahrens. Directed and choreographed by Marcia Milgrom Dodge. Neil Simon Theatre, New York City. 22 November 2009. When the original production of the musical Ragtime closed on Broadway in early 2000, after a two-year run that many fans, including me, called too short, the high cost of running the large-scale, opulent show was blamed. Thus it seemed foolhardy to bring Ragtime, based on the E. L. Doctorow novel, back to Broadway in late 2009, when the economy was only starting to recover after the latest recession—and, in fact, the new production ran for less than two months. Despite this premature closure, the revival of Ragtime offers valuable lessons in how to do a big musical well, even when money is tight. By utilizing regional theatre as a development platform and privileging concept over spectacle and character over star power (both onstage and behind the scenes), Ragtime created a new paradigm for producing large-scale, professional musicals in economically troubled times. Ragtime's road back to Broadway began in regional theatre during the spring of 2009 with a successful Kennedy Center run, also helmed by director/choreographer Marcia Milgrom Dodge. The musical, which depicts a cross-section of American life at the dawn of the twentieth century and features music by Stephen Flaherty and lyrics by Lynn Ahrens, transferred nearly intact to Broadway, which makes financial sense, since resources like talent, sets, and costumes were effectively recycled and reused. Also, because the Kennedy Center is removed from the higher costs and immediate pressure for success (both artistic and financial) associated with Broadway, it both provided Ragtime with a less expensive and more nurturing development period, and served as an out-of-town tryout that could placate jittery Broadway investors. The current financial climate played a key role not only in Ragtime's out-of-town development, but also in its production concept and execution. Terrence McNally's libretto already stripped the epic novel to its essentials, and Dodge took that a step further in her vision of a simplified and suggested, rather than realistically represented, story. Click for larger view View full resolution The opening tableau of Ragtime. (Photo: Joan Marcus.) [End Page 460] Click for larger view View full resolution Christiane Noll (Mother) in Ragtime. (Photo: Joan Marcus.) [End Page 461] This shifted the focus to the gloriously sung music, which clearly depicted both the dawning of a new era (in the haunting "New Music") and the revolutionary power of music to transcend traditional boundaries (in the moving funeral march "Till We Reach That Day"). Unfortunately, Ragtime is long on rousing anthems, and the scaled-back spectacle revealed the structural flaws that caused the pace of the show to drag, particularly in act 2. Of course, less emphasis on spectacle does not mean that the design was less than impressive; in fact, the set, designed by Derek McLane, evoked a large, arched, multilevel metal structure reminiscent of New York's original Penn Station, which easily stood in for a variety of locations. At times, this style was enormously successful—as when a bare metal frame, rather than an actual Model T Ford, was used as the ill-fated car owned by black ragtime musician turned revolutionary, Coalhouse Walker Jr. Unfortunately, at other times it was far less successful, as when Dodge and McLane chose to reuse certain set pieces to denote multiple places. For example, in the baseball-centric "What a Game!" the bleachers were created by having the cast awkwardly stack together the elegant dining-room furniture just used by the privileged, white Mother and her family, which created a jarring sequence in a number that already felt like it wandered in from another musical. In addition, judicious pruning, presumably in the service of simplification, rendered some sequences, such as Coalhouse's escalating campaign of retribution against the firemen, difficult to follow for audiences not already familiar with the musical. In spite of these weaknesses, however, the simpler approach (probably spawned by the recession) generally improved rather than detracted from...

Superconformal Electrodeposition for 3‐Dimensional Interconnects

AbstractElectrodeposition is a key fabrication process used in the state‐of‐the‐art multilevel Cu metallization of microelectronic interconnects, from transistor to circuit board length scale. Recent electrochemical surface science and feature filling studies have provided mechanistic insight into the role of additives in superconformal film growth responsible for void‐free filling of recessed surface features. These studies have shown that a physical model based on mass conservation of accelerating surfactant species during area change very effectively describes feature filling of Cu, Ag, and Au from different electrolytes. This paper presents a selective and cursory review of some relevant developments underway in our laboratory.

Electrical Demonstration of TSV Interconnects and Multilevel Metallization for 3D Si Interposer Applications

A TSV test vehicle lot and 3D interposer demonstration lot were successfully fabricated and tested. Fabrication of the TSV test vehicle was accomplished using three process (mask) levels – front-side metal, backside TSV, and backside metal. The TSVs were formed using a vias-last approach with a nominal TSV size of 100μm, and an aspect ratio of 6:1. DRIE bottom clear process conditions were tested which produced 100 % yield on TSV contact chains with up to 540 vias. In addition, optimum process conditions resulted in a TSV resistance of 29 mΩ, and sufficient TSV isolation resistance (> 1MΩ) for the target application. The interposer demonstration lot incorporated five front-side metal levels, one TSV level, and two backside metal levels. The first four metal layers (M1-M4), utilized 2μm Cu and 2μm oxide layers. Metal layers M2-M4 were fabricated using a self-aligned dual damascene process. Each wafer in the demonstration lot had 4 MLM contact chain test structures, with 26400 vias per structure. On two wafers, 100 % yield was achieved on the MLM contact chains. For the dual damascene levels, average contact resistance per via was 4 mΩ. Functional testing was performed on two die from the demonstration lot (die size = 4 cm X 3.7 cm). Over 99 % of the functional nets (circuit paths) passed. Yield on large area test capacitors, tested at wafer level, exceeded 80 %.

Nano- and micrometer-scale thin-film-interconnection failure theory and simulation and metallization lifetime prediction, Part 1: A general theory of vacancy transport, mechanical-stress generation, and void nucleation under electromigration in relation to multilevel-metallization degeneration and failure

The physical principles are considered of on-chip interconnection degeneration and failure in sub-1-µm technologies from the viewpoint of multilevel-metallization reliability. A general theory and simulation results are presented that deal with electromigration-induced failure of thin-film conducting tracks on the micro- and nanometer scales. They provide a detailed treatment of micro-, meso-, and nanoscopic mechanisms underlying the deformation and breaking of actual interconnection configurations. Parts 1 and 2 contain (i) the derivation and analysis of basic kinetic equations; (ii) the formulation and solution of three-dimensional boundary-value problems representing the transport of vacancies (both in the bulk and along grain boundaries) and the development of deformation and stress; (iii) models of void nucleation and development; (iv) an analysis of a multilevel-metallization lifetime; and (v) the identification of potential break locations in a multilevel metallization in relation to current density, metallization structure and layout, temperature, and the grain structure of the conducting material. Part 3 deals with electromigration in doped on-chip polycrystalline interconnections in terms of lengthening their lifetime. To predict electromigration resistance, models are constructed that represent the influence of texture and other grain-boundary properties on the effective charges of native and dopant ions.

Interlevel Dielectric Processes Using PECVD Silicon Nitride, Polyimide, and Polybenzoxazole for GaAs HBT Technology

Multiple factors need to be considered when selecting an interlevel dielectric material for GaAs semiconductor device fabrication including what the electrical, mechanical, chemical, thermal, and cost requirements are and whether the material and the process are compatible with GaAs processing. In this study, we evaluated several interlevel dielectric materials for GaAs heterojunction bipolar transistor (HBT) technology. This technology requires the material to have good gapfill and planarizing characteristics, as the various device and interconnect structures can have significant topography. Additionally, the process typically can only have a maximum temperature of , as device degradation can occur at higher temperatures. The dielectric materials evaluated are plasma-enhanced chemical vapor deposition (PECVD), silicon nitride , polyimide, and photodefinable polybenzoxazole (PBO). The PECVD is mostly conformal when deposited. However, it has a high dielectric constant, cannot be used as gapfill material, and does not planarize the underlying topography, which makes multilevel metallization challenging. Polyimide and PBO, both of which need to be thermally cured, have a lower dielectric constant than PECVD . However, the polyimide in this study has to be dry-etched, unlike the photosensitive PBO. Furthermore, the PBO has better gapfill and planarization capabilities than polyimide.

InP DHBT Process in Transferred-Substrate Technology With $f_{t}$ and $f_{\max}$ Over 400 GHz

In this paper, a double heterojunction bipolar transistor (DHBT) process has been developed in transferred-substrate (TS) technology to optimize high-frequency performance. It provides an aligned lithographic access to frontside and backside of the device to eliminate dominant transistor parasitics. The transistors of 0.8 times 5-mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> emitter mesa feature f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> = 410 GHz and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> = 480 GHz at a BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ceo</sub> = 5.5 V. Parallel to the device setup, a multilevel metallization scheme is established. It serves as construction kit for 3-D configurations of active and passive elements. High yield of the TS DHBTs, consistent large-signal modeling, and accurate simulation of complex passive elements have been demonstrated and have proved the availability of the technology for advanced millimeter-wave circuit design.

Investigation of stress distribution in via bottom of Cu-via structures with different via form by means of submodeling

In ULSI multilevel metallizations the via bottom is the main region for the appearance of local stress. This local stress can lead to fractures or porous spots. Out of this concerning the local stress distribution the via bottom region has to be investigated. Due to various technological processes the via shape especially the via bottom geometries are different. In this paper FE-Simulations with respect to the different via bottom geometries and different temperatures of the process steps will be presented. The best via bottom geometry is figured out. The submodeling technique in ANSYS ® is used for these investigations for reduction of simulation time and precise results. The thickness of the barrier has also an influence on the mechanical stress and will be also investigated.

32 nm node BEOL integration with an extreme low- k porous SiOCH dielectric k = 2.3

A 32 nm node BEOL integration scheme is presented with 100 nm metal pitch at local and intermediate levels and 50 nm via size through a M1-Via1-M2 via chain demonstrator. To meet the 32 nm RC performance specifications, extreme low- k (ELK) porous SiOCH k = 2.3 is introduced at line and via level using a Trench First Hard Mask dual damascene architecture. Parametrical results show functional via chains and good line resistance. Integration validation of ELK porous SiOCH k = 2.3 is investigated using a multi-level metallization test vehicle in a 45 nm mature generation.

Comparison of Interlevel Dielectric Processes Using PECVD Silicon Nitride, Polyimide, and Polybenzoxazole for GaAs HBT Technology

In this study, we have evaluated several interlevel dielectric materials for GaAs hetero-junction bipolar transistor (HBT) technology. This technology requires the material to have good gapfill and planarizing characteristics, as the various device and interconnect structures can have significant topography. Additionally, the process typically can only have a maximum temperature of <300oC, as device degradation can occur at higher temperatures. The dielectric materials evaluated are PECVD silicon nitride (Si3N4), polyimide, and photodefinable polybenzoxazole (PBO). The PECVD Si3N4 is mostly conformal when deposited. However, it has a high dielectric constant, cannot be used as gapfill material, and does not planarize the underlying topography, which makes multilevel metallization challenging. Polyimide and PBO, both of which need to be thermally cured, have lower dielectric constant than PECVD Si3N4. However, the polyimide has to be dry-etched, unlike the photosensitive PBO. Furthermore, the PBO has better gapfill and planarization capabilities than polyimide.

Application of Six Sigma Methodology to Optimize the Performance of the Inter-Metal Dielectric Process

As semiconductor device density increases, integrated circuits generally involve more levels of metallization. In multilevel interconnected metallization schemes, an inter-metal dielectric (IMD) is deposited between metal layers. The basic advantage of this dielectric layer is that it provides good step coverage to help smooth the topology, making it free of pinholes and allowing it to act as a good insulator. The key problem in the IMD layer is the occurrence of voids which may cause electric leakage and later result in yield loss. The occurrence of these voids may be avoided by ensuring an excellent gap-fill capacity. Taking this into consideration, improving the gap-fill capacity is one of the critical issues for the IMD layer. In addition, the quantity of fluorine and the value of voltage ramping to dielectrics breakdown (VRDB) also affect the quality of the IMD layer. The gap-fill capacity, VRDB, and the quantity of fluorine are important quality characteristics for the optimization of the performance of the IMD layer. Due to the complicated inputs/responses relation, it is difficult for the output of the IMD process to reach the desired target. To resolve this problem, this study employs the Six Sigma methodology to reduce the defect in the IMD layer. A case study of a semiconductor manufacturing foundry in Taiwan is illustrated to show the practicability of the Six Sigma methodology.