Multilevel Charge Storage Research Articles

Multilevel Charge Storage in a Multiple Alloy Nanodot Memory

A multilevel charge storage in a multiple FePt alloy nanodot memory is investigated for the first time. It is demonstrated that the memory structure with multiple FePt nanodot layers effectively realizes a multilevel state by the adjustment of gate voltage. Metal oxide semiconductor (MOS) capacitors with four FePt nanodot layers as a floating gate are fabricated to evaluate the multilevel cell characteristic and reliability. Here, the effect of memory window for a nanodot diameter is also investigated, and it is found that a smaller dot size gives a larger window. From the results showing good endurance and retention characteristics for the multilevel states, it is expected that a multiple FePt nanodot memory using Fowler–Nordheim (FN) tunneling can be a candidate structure for the future multilevel NAND flash memory.

Synthesis and charge storage properties of double-layered NiSi nanocrystals

Based on bidirectional diffusion of Ni atoms, double-layered nickel silicide (NiSi) nanocrystals (NCs) for multilevel charge storage were fabricated, and their charge storage properties were examined. The double layer was produced by long-term thermal annealing (for 4 h at 900 °C) of a sandwich structure comprised of a thin Ni film of 0.3 nm sandwiched between two silicon-rich oxide (SiO1.36) layers. Transmission electron microscopic image clearly exhibits a distinct NiSi nanocrystal double layer with a gap of about 7 nm between the mean positions of particle distribution in each NC layer. Capacitance–voltage measurements on the metal/oxide/semiconductor (MOS) capacitors with the double-layered NiSi nanocrystals are shown to have the apparent two plateaus of charge storage, the large memory window of about 9 V and the improved charge retention stability.

Multilevel charge storage in Si nanocrystals arranged in double-dot-layers within SiO 2

We investigated charging/discharging characteristics of a MOS structure with two layers of Si-nanocrystals (NCs) embedded in the SiO 2 dielectric. The two-dimensional (2D) arrays of nanocrystals, of sizes 3 and 5 nm in the lower and upper NCs layer, respectively, were fabricated by low pressure chemical vapor deposition (LPCVD) of amorphous Si (a-Si), followed by oxidation/annealing. The tunnel oxide was 3.5 nm thick. Successive charging of the NCs layers by both electrons and holes injected from the substrate was clearly demonstrated by the observed steps in the flatband voltage shift (Δ V FB) as a function of the applied positive (electrons) or negative (holes) pulses on the gate, thus opening the potential for multiple bit operation of the memory. Discharging of the structure by pulses of opposite sign was consistently obtained. The current–voltage ( I– V) curves exhibited two transient peaks at voltages corresponding to the two steps in Δ V FB vs. V gate that were attributed to a displacement current from the substrate to the nanocrystal layers. Clear improvement of charge retention in the double-nanocrystal layer structure compared to the single one was obtained, opening the possibility for lowering the gate oxide thickness of the NC memory without compromising device reliability.

Pd-nanocrystal-based nonvolatile memory structures with asymmetric SiO2∕HfO2 tunnel barrier

Pd nanocrystals (NCs) on asymmetric tunnel barrier (ATB) composed of stacked SiO2 and HfO2 layers have been employed for nonvolatile memory devices. The Pd-NC layers are formed by electrostatic self-assembly of negatively charged colloidal Pd NCs. The presence of isolated Pd NCs of ∼5nm embedded in HfO2 is confirmed by scanning and transmission electron microscopy images. Outstanding program∕erase (P∕E) properties from C-V curves are observed with a memory window of 6V under ±17V. Extrapolation of the data up to ten years shows that the flatband voltage drops at the P∕E levels are maintained within only 1.0∕0.5V, respectively, resulting from the efficient data retention based on the ATB. These results are promising enough for the memory structure to be utilized for the multilevel charge storage.

Quasi-Superlattice Storage: A Concept of Multilevel Charge Storage

In this work, a novel concept of quasi-superlattice storage (QS2) is demonstrated. Under a suitable operating voltage, two apparent states of charge storage can be distinguished. The memory effects are due to the multilevel charge storage within the quasi-superlattice. The multilevel charge storage provides a feasible design for the 2-bit-per-cell nonvolatile memory devices. Also, the leakage behavior of the quasi-superlattice structure has also been characterized by current-voltage measurements at room temperature and low temperatures. The resonant tunneling-like leakage characteristic is observed at low temperatures. A concise physical model is proposed to characterize the leakage mechanism of tunneling for the quasi-superlattice structure, and this suggests that consideration of the operating voltage for the 2-bit-per-cell nonvolatile memory device needs to be taken into account. © 2004 The Electrochemical Society. All rights reserved.

Quasisuperlattice storage: A concept of multilevel charge storage

A concept of the quasisuperlattice storage has been demonstrated in this study. Under suitably operated voltage, two apparent states of charge storage can be distinguished. The memory effects are due to the multilevel storage in the quasisuperlattice. Also, the a-Si quantum wells provide a feasible design for the 2 bit per cell nonvolatile memory devices. The operation of the 2 bit per cell needs to be performed by Fowler–Nordheim tunneling instead of conventional channel hot electron injection. Additionally, the dual read operation of the source and drain sides for conventional SONOS 2bit∕cell device is not necessary, which simplifies the circuit design engineering.

Leakage behavior of the quasi-superlattice stack for multilevel charge storage

The leakage behavior of the quasi-superlattice structure has been characterized by current–voltage measurements at room temperature and 50 K. A resonant tunnelinglike leakage characteristic is observed at low temperature. The resonant tunneling occurs at around 2, 5.2, and 7 V under a gate voltage swept from 0 to 10 V. A concise physical model is proposed to characterize the leakage mechanism of tunneling for the quasi-lattice structure and suggests that the considerations of the operating voltage for the two-bit per cell nonvolatile-memory device need to be taken into account.

Voltage variant source side injection for multilevel charge storage in flash EEPROM

The growing demand for high-density Flash memories in portable computing, smart cards, and telecommunications applications has boosted the efforts on Flash memory cell size scaling and cost reduction. In order to further increase the storage capability and, consequently, reduce the cost per bit of Flash memories, multilevel charge storage (MLCS) techniques have recently gained a lot of interest. Furthermore, MLCS is considered a viable route for increasing embedded Flash density as well. The devices investigated so far, rely either on conventional channel hot electron (CHE) injection or on Fowler-Nordheim tunneling (FNT) for programming. For the first time, this paper shows that source side injection (SSI) is also an excellent candidate for MLCS. The main advantages of SSI for MLCS are the very narrow threshold-voltage distributions after SSI programming, the symmetrical threshold-voltage window and the overerase immunity, which allows an overall wider threshold-voltage window, and hence more separated distributions.