Multi-core Environment Research Articles

Performance Optimization on Multi-Core Processors and Windows 11 Kernel Management

Multi-core processors have become the primary solution to improve processing performance by dividing tasks across multiple processing cores. This study analyzes the performance of two operating systems with the same hardware. Parameters such as boot time, CPU usage, memory efficiency, and application performance are tested through Pass Mark Performance Test and Geekbench. The method used in this study uses a quantitative approach with an experimental method. This approach was chosen to analyze and measure system performance objectively through controlled testing. The test results include boot time, processor workload distribution, memory efficiency, and application responsiveness. The results show that Windows 11 has a faster boot time, a more even distribution of processor workload, and increased memory efficiency. In addition, virtualization-based security (VBS) makes applications more responsive. Therefore, Windows 11 is the best option for high-performance multicore environments.

A High Performance Parallel Approach to Delay Sum Beamformer in a Homogeneous Multicore Environment

A Cache-Aware Beamformer (CABF) algorithm for the DAS beamformer in a homogeneous multicore processor environment is presented. The context of the proposed algorithm is established by discussing the case for a refined multicore implementation of the beamformer algorithm for a sonar application. The algorithm is designed, implemented, and compared to a regular pthread multicore implementation and a standard OpenMP-based implementation, using arithmetic intensity as the metric. FMA implementations of the algorithms are carried out, and the CABF algorithm is shown to achieve a better arithmetic intensity. A 6000-element array is designed with a simultaneous forming of 200 beams to test the efficacy of cabf in a multicore platform. The results show a 73 % increase in GFLOPS for FMA operations. The performance of the beamformer algorithm for different data sizes is studied, and on average, a 36 % improvement in computational performance is achieved compared to the OpenMP-based implementation.

A Parallel Approach to Enhance the Performance of Supervised Machine Learning Realized in a Multicore Environment

Machine learning models play a critical role in applications such as image recognition, natural language processing, and medical diagnosis, where accuracy and efficiency are paramount. As datasets grow in complexity, so too do the computational demands of classification techniques. Previous research has achieved high accuracy but required significant computational time. This paper proposes a parallel architecture for Ensemble Machine Learning Models, harnessing multicore CPUs to expedite performance. The primary objective is to enhance machine learning efficiency without compromising accuracy through parallel computing. This study focuses on benchmark ensemble models including Random Forest, XGBoost, ADABoost, and K Nearest Neighbors. These models are applied to tasks such as wine quality classification and fraud detection in credit card transactions. The results demonstrate that, compared to single-core processing, machine learning tasks run 1.7 times and 3.8 times faster for small and large datasets on quad-core CPUs, respectively.

Solving Traveling Salesman Problem Using Parallel River Formation Dynamics Optimization Algorithm on Multi-core Architecture Using Apache Spark

According to Moore’s law, computer processing hardware technology performance is doubled every year. To make effective use of this technological development, the algorithmic solutions have to be developed at the same speed. Consequently, it is necessary to design parallel algorithms to be implemented on parallel machines. This helps to exploit the multi-core environment by executing multiple instructions simultaneously on multiple processors. Traveling Salesman (TSP) is a challenging non-deterministic-hard optimization problem that has exponential running time using brute-force methods. TSP is concerned with finding the shortest path starting with a point and returning to that point after visiting the list of points, provided that these points are visited only once. Meta-heuristic optimization algorithms have been used to tackle TSP and find near-optimal solutions in a reasonable time. This paper proposes a parallel River Formation Dynamics Optimization Algorithm (RFD) to solve the TSP problem. The parallelization technique depends on dividing the population into different processors using the Map-Reduce framework in Apache Spark. The experiments are accomplished in three phases. The first phase compares the speedup, running time, and efficiency of RFD on 1 (sequential RFD), 4, 8, and 16 cores. The second phase compares the proposed parallel RFD with three parallel water-based algorithms, namely the Water Flow algorithm, Intelligent Water Drops, and the Water Cycle Algorithm. To achieve fairness, all algorithms are implemented using the same system specifications and the same values for shared parameters. The third phase compares the proposed parallel RFD with the reported results of metaheuristic algorithms that were used to solve TSP in the literature. The results demonstrate that the RFD algorithm has the best performance for the majority of problem instances, achieving the lowest running times across different core counts. Our findings highlight the importance of selecting the most suitable algorithm and core count based on the problem characteristics to achieve optimal performance in parallel optimization.

A Detailed Study of SOT-MRAM as an Alternative to DRAM Primary Memory in Multi-Core Environment

A Detailed Study of SOT-MRAM as an Alternative to DRAM Primary Memory in Multi-Core Environment

A parallel preconditioning Schur complement approach for large scale industrial problems

The purpose of this paper is to introduce a new strategy to improve the convergence and efficiency of the class of domain decomposition known as Schur complement techniques related to interface variables for the simulation of mechanical, electrical and thermal problems in presence of cross points. More precisely, we are interested not only in domain decomposition with two equal parts having the same physical properties but rather in more general splitting components. It is known that in the first case, the optimal convergence with good pre-conditioner is obtained in two iterations and the problem is still challenging in the second case. The primary goal then is to fill part of the gap in such problem domain decomposition techniques and to contribute to solve extremely difficult industrial problems of large scale by using parallel sparse direct solver of the multi-core environment of the whole system and handling each part of the system independently of the change of the mesh or the shifting of the mathematical method of resolution and subsequently, we treat the interface as boundary conditions. The numerical experiments of our algorithm are performed on few models arising from discretization of partial differential equations using Finite Element Method (FEM).

Symmetry-based decomposition for optimised parallelisation in 3D printing processes

Current research in 3D printing focuses on improving printing performance through various techniques, including decomposition, but targets only single printers. With improved hardware costs increasing printer availability, more situations can arise involving a multitude of printers, which offers substantially more throughput in combination that may not be best utilised by current decomposition approaches. A novel approach to 3D printing is introduced that attempts to exploit this as a means of significantly increasing the speed of printing models. This was approached as a problem akin to the parallel delegation of computation tasks in a multi-core environment, where optimal performance involves computation load being distributed as evenly as possible. To achieve this, a decomposition framework was designed that combines recursive symmetric slicing with a hybrid tree-based analytical and greedy strategy to optimally minimise the maximum volume of subparts assigned to the set of printers. Experimental evaluation of the algorithm was performed to compare our approach to printing models normally (“in serial”) as a control. The algorithm was subjected to a range of models and a varying quantity of printers in parallel, with printer parameters held constant, and yielded mixed results. Larger, simpler, and more symmetric objects exhibited more significant and reliable improvements in fabrication duration at larger amounts of parallelisation than smaller, more complex, or more asymmetric objects.

Vectorized and Parallel Computation of Large Smooth-Degree Isogenies using Precedence-Constrained Scheduling

Strategies and their evaluations play important roles in speeding up the computation of large smooth-degree isogenies. The concept of optimal strategies for such computation was introduced by De Feo et al., and virtually all implementations of isogeny-based protocols have adopted this approach, which is provably optimal for single-core platforms. In spite of its inherent sequential nature, several recent works have studied ways of speeding up this isogeny computation by exploiting the rich parallelism available in vectorized and multi-core platforms. One obstacle to taking full advantage of this parallelism, however, is that De Feo et al.’s strategies are not necessarily optimal in multi-core environments. To illustrate how the speed of vectorized and parallel isogeny computation can be improved at the strategylevel, we present two novel software implementations that utilize a state-of-the-art evaluation technique, called precedence-constrained scheduling (PCS), presented by Phalakarn et al., with our proposed strategies crafted for these environments. Our first implementation relies only on the parallelism provided by multi-core processors. The second implementation targets multi-core processors supporting the latest generation of the Intel’s Advanced Vector eXtensions (AVX) technology, commonly known as AVX-512IFMA instructions. To better handle the computational concurrency associated with PCS, we equip both implementations with extensive synchronization techniques. Our first implementation outperforms the implementation of Cervantes-Vázquez et al. by yielding up to 14.36% reduction in the execution time, when targeting platforms with two- to four-core processors. Our second implementation, equipped with four cores, achieves up to 34.05% reduction in the execution time compared to the single-core implementation of Cheng et al. of CHES 2022.

A Batched Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-Fidelity Modeling

Device sizing is a challenging problem for analog circuit design. Traditional methods depend on domain knowledge and intensive simulations to search for feasible parameters. Recent studies apply the Bayesian optimization (BO) and a Gaussian process (GP) model in analog circuit synthesis to improve efficiency. The BO framework automatically selects the parameter candidates by inferring the surrogate GP model. However, naive BO employs a sequential updating strategy which is inefficient in a multicore environment. Besides, the widely used GP model requires costly high fidelity data, which are obtained from fine simulations. In this article, we propose a constrained batch BO approach with a multifidelity (MF) model to solve the above difficulties. The batch BO exploits parallel computing and selects promising parameters by multiple acquisition function ensemble. In addition, the MF GP model adapts the low fidelity data obtained from coarse simulations. Specifically, the proposed method incorporates information gain in a weighted clustering algorithm to refine the parameter candidates. As a result, the proposed method maintains the candidates’ quality and diversity, which speeds up the optimization convergence. In the experiments, we demonstrate the efficiency of the proposed approach on three real-world circuits. The results show that our approach reduces the simulation costs by at least 54.6% compared to the state-of-the-art baselines.

PARALLEL PROCESSING OUTCOMES OF E-ABDULRAZZAQ ALGORITHM USING MULTI-CORE TECHNIQUE

The string matching problem is considered one of the substantial problems in the fields of computer science like speech and pattern recognition, signal and image processing, and artificial intelligence (AI). The increase in the speedup of performance is considered an important factor in meeting the growth rate of databases, Subsequently, one of the determinations to address this issue is the parallelization for exact string matching algorithms. In this study, the E-Abdulrazzaq string matching algorithm is chosen to be executed with the multi-core environment utilizing the OpenMP paradigm which can be utilized to decrease the execution time and increase the speedup of the algorithm. The parallelization algorithm got positive results within the parallel execution time, and excellent speeding-up capabilities, in comparison to the successive result. The Protein database showed optimal results in parallel execution time, and when utilizing short and long pattern lengths. The DNA database showed optimal speedup execution when utilizing short and long pattern lengths, while no specific database obtained the worst results.

Multicore Quantum Computing

Any architecture for practical quantum computing must be scalable. An attractive approach is to create multiple cores, computing regions of fixed size that are well-spaced but interlinked with communication channels. This exploded architecture can relax the demands associated with a single monolithic device: the complexity of control, cooling and power infrastructure as well as the difficulties of cross-talk suppression and near-perfect component yield. Here we explore interlinked multicore architectures through analytic and numerical modelling. While elements of our analysis are relevant to diverse platforms, our focus is on semiconductor electron spin systems in which numerous cores may exist on a single chip. We model shuttling and microwave-based interlinks and estimate the achievable fidelities, finding values that are encouraging but markedly inferior to intra-core operations. We therefore introduce optimsed entanglement purification to enable high-fidelity communication, finding that $99.5\%$ is a very realistic goal. We then assess the prospects for quantum advantage using such devices in the NISQ-era and beyond: we simulate recently proposed exponentially-powerful error mitigation schemes in the multicore environment and conclude that these techniques impressively suppress imperfections in both the inter- and intra-core operations.

Limited-memory common-directions method for large-scale optimization: convergence, parallelization, and distributed optimization

In this paper, we present a limited-memory common-directions method for smooth optimization that interpolates between first- and second-order methods. At each iteration, a subspace of a limited dimension size is constructed using first-order information from previous iterations, and an efficient Newton method is deployed to find an approximate minimizer within this subspace. With properly selected subspace of dimension as small as two, the proposed algorithm achieves the optimal convergence rates for first-order methods while remaining a descent method, and it also possesses fast convergence speed on nonconvex problems. Since the major operations of our method are dense matrix-matrix operations, the proposed method can be efficiently parallelized in multicore environments even for sparse problems. By wisely utilizing historical information, our method is also communication-efficient in distributed optimization that uses multiple machines as the Newton steps can be calculated with little communication. Numerical study shows that our method has superior empirical performance on real-world large-scale machine learning problems.

Effectiveness Evaluation of Replacement Policies for On-Chip Caches in Multiprocessors

A Cache plays a vital role in improving performance in the multicore environment, especially the Last Level Cache (LLC). The improvements in performance are based on the block size, associativity, and replacement policies. Most of the papers concentrate on traditional Least Recently Used (LRU) based replacement policies for their replacement decisions. Unfortunately, the replacement decisions do not enhance performance of the cache as expected. An enhanced modified Pseudo LRU policy is proposed, which is an approximation of LRU. The proposed methodology uses counters to enhance the confidence of replacement decisions based on the history of the replaceable blocks in cache. It is very clear from the Simulation results that the replacement scheme proposed exhibits better performance improvement in terms of miss ratio of about 3% and energy efficiency of about 2% on an average.

Energy-Efficient Cache-Aware Scheduling on Heterogeneous Multicore Systems

The adoption of heterogeneous multicore architectures into deadline-constrained embedded systems has various benefits in terms of schedulability and energy-efficiency. Existing energy-efficient algorithms, in this domain, allocate tasks to their energy-favorable core-types while using dynamic voltage and frequency scaling to reduce energy consumption. However, the practicality of such algorithms is limited due to the underlying assumptions made to simplify the analysis. This article paves the way for more practical approaches to minimize the energy consumption on heterogeneous multicores. Specifically, we investigate the nonlinear impacts that core-frequency and cache-partitioning have on task-executions in a heterogeneous multicore environment. In doing so, we propose an algorithm that exploits this relationship to effectively allocate tasks to specific cores and core-types, and determine the number of cache-partitions for each core. Extensive simulations using real-world benchmarks show the proficiency of our approach by achieving an average and maximum energy savings of 14.9 and 20.4 percent, respectively for core-level energy consumption, and 20.2 and 60.4 percent, respectively for system-level energy consumption.

Application of Gabor Image Recognition Technology in Intelligent Clothing Design

Aiming at the complex problem of image recognition feature extraction, this paper proposes an intelligent clothing design model based on parallel Gabor image feature extraction algorithm. Based on the intelligent parallel mode, the algorithm decomposes and merges the calculation process of the image Gabor transformation, decomposes the entire image Gabor feature extraction calculation process into a parallel part and a nonparallel part, and accelerates the parallel part by using multiple cores. The calculation results are then combined to achieve the purpose of multicore parallel acceleration of the entire calculation process. Secondly, based on the consideration of improving the real-time performance of the intelligent clothing design system, combined with the existing multicore environment, this paper uses the intelligent model to design and implement the image parallel Gabor feature extraction algorithm and uses image processing and analysis technology to analyze the visual elements of traditional clothing and identify and quantify to form a relatively complete clothing visual element evaluation system, which provides a basis for large-scale collection and automated evaluation of clothing visual effects, as well as clothing trend tracking and prediction. Experiments show that the algorithm can effectively shorten the calculation time of Gabor image feature extraction and can obtain a good speedup in a multicore environment. At the same time, it combines with a multiscale intelligent clothing classification algorithm, on the basis of the VS2008 platform, combined with OpenCV 2.0, designed and implemented an intelligent clothing design system, and conducted experiments and system tests. The experimental results show that the algorithm given in this paper can accurately segment fabric defects from the background, which proves that the detection algorithm has a good detection effect. Simulation results show that the algorithm proposed in this paper can more accurately identify the state of clothing features, and the real-time performance of intelligent clothing design in a multicore environment has been improved to a certain extent.

Parallelizing filter-and-verification based exact set similarity joins on multicores

Set similarity join (SSJ) is a well studied problem with many algorithms proposed to speed up its performance. However, its scalability and performance are rarely discussed in modern multicore environments. Existing algorithms assume a single-threaded execution that leaves the abundant parallelism provided by modern machines unused, or use distributed setups that may not yield efficient runtimes and speedups that are proportional to the amount of hardware resources (e.g., CPU cores). In this paper, we focus on a widely-used family of SSJ algorithms that are based on the filter-and-verification paradigm, and study the potential of speeding them up in the context of multicore machines. We adapt state-of-the-art SSJ algorithms including PPJoin and AllPairs. Our experiments using 12 real-world datasets highlight important findings: (1) Using the exact number of hardware-provided hyperthreads leads to optimal runtimes for most experiments, (2) hand-crafted data structures do not always lead to better performance, and (3) PPJoin’s position filter is more effective in the multithreaded case compared to the single-threaded execution.

Origami

Mergesort is a popular algorithm for sorting real-world workloads as it is immune to data skewness, suitable for parallelization using vectorized intrinsics, and relatively simple to multi-thread. In this paper, we introduce Origami , an in-memory merge-sort framework that is optimized for scalar, as well as all current SIMD (single-instruction multiple-data) CPU architectures. For each vector-extension set (e.g., SSE, AVX2, AVX-512), we present an in-register sorter for small sequences that is up to 8× faster than prior methods and a branchless streaming merger that achieves up to a 1.5× speed-up over the naive merge. In addition, we introduce a cache-residing quad-merge tree to avoid bottlenecking on memory bandwidth and a parallel partitioning scheme to maximize thread-level concurrency. We develop an end-to-end sort with these components and produce a highly utilized mergesort pipeline by reducing the synchronization overhead between threads. Single-threaded Origami performs up to 2× faster than the closest competitor and achieves a nearly perfect speed-up in multi-core environments.

Two Birds With One Stone: Boosting Both Search and Write Performance for Tree Indices on Persistent Memory

The advance of byte-addressable persistent memory (PM) makes it a hot topic to revisit traditional tree indices such as B+-tree and radix tree, and a few new persistent memory-friendly tree indices have been proposed. However, due to the special features of persistent memory compared to DRAM and the limitations of B+-tree-like indices, it is much harder to optimize both search and write performance for tree indices on persistent memory. As a result, most existing indices for persistent memory, e.g., WB-tree, proposed to improve write performance while sacrificing search performance. Aiming to optimize both write and search performance for tree indices on persistent memory, in this paper, we first propose a novel Two-Layer Architecture (TLA) for constructing tree indices on persistent memory. The key idea, of TLA is to organize the index with a search-optimized top layer and a write-optimized bottom layer, letting the top layer optimize search performance and the bottom layer improve write performance. By adopting efficient structures for the two layers, TLA can boost both write and search performance for tree indices on persistent memory. Following the TLA architecture, we present a new index called TLBtree (Two-Layer B+-tree) offering high search and write performance for persistent memory. Moreover, we develop a concurrent TLBtree to support non-blocking read operations in multi-core environment. We evaluate our proposals under a server equipped with real Intel Optane persistent memory. The results show that TLBtree outperforms the state-of-the-art tree indices, including WB-tree, Fast&Fair, and FPTree, in both search and write performance. Also, the concurrent TLBtree can achieve up to 3.7x speedup than its competitors under the multi-core environment.

Improving the performance of bagging ensembles for data streams through mini-batching

Often, machine learning applications have to cope with dynamic environments where data are collected in the form of continuous data streams with potentially infinite length and transient behavior. Compared to traditional (batch) data mining, stream processing algorithms have additional requirements regarding computational resources and adaptability to data evolution. They must process instances incrementally because the data’s continuous flow prohibits storing data for multiple passes. Ensemble learning achieved remarkable predictive performance in this scenario. Implemented as a set of (several) individual classifiers, ensembles are naturally amendable for task parallelism. However, the incremental learning and dynamic data structures used to capture the concept drift increase the cache misses and hinder the benefit of parallelism. This paper proposes a mini-batching strategy that can improve memory access locality and performance of several ensemble algorithms for stream mining in multi-core environments. With the aid of a formal framework, we demonstrate that mini-batching can significantly decrease the reuse distance (and the number of cache misses). Experiments on six different state-of-the-art ensemble algorithms applying four benchmark datasets with varied characteristics show speedups of up to 5X on 8-core processors. These benefits come at the expense of a small reduction in predictive performance.

Parallel implementation of maximum-shift algorithm using OpenMp

String matching is considered as one of the center issues within the field of computer science, where there are numerous computer applications that supply the clients with string matching services. The increment within the number of databases which are created and protected in numerous computer gadgets had impacted researchers with the slant towards getting robust techniques in tending to this issue. In this study, the Maximum-Shift string matching algorithm is chosen to be executed with multi-core innovation through the utilization of OpenMP paradigm, in order to decrease the successive time, and increment the speedup and efficiency of the algorithm. The deoxyribonucleic acid (DNA), protein and the English text datasets are utilized to test the parallel execution that influences the Maximum-Shift algorithm execution when utilized with multi-core environment. The results demonstrated that the execution is affected by the performance between the parallel and consecutive execution of Maximum-Shift algorithm by data type. The English text appeared ideal comes about within the parallel execution time as compared to other datasets, whereas the DNA database set appeared the most elevated comes about when compared to other data types in terms of speedup and efficiency capabilities.