Multi-core Environment Research Articles

A Compensated Distributed-Parameter Line Decoupling Approach for Real Time Applications

This article proposes a new method called the Compensated Distributed-Parameter Line Decoupling (CDLD) method, and used for decoupling distribution networks among parallel processing cores in a real-time multi-core environment. Due to the short length of distribution grid lines, decoupling the distribution network for real-time processing is challenging and approaches such as Stublines and State Space Nodal (SSN) solvers have been proposed. Both approaches have limitations and the method proposed in this work addresses these limitations to implement improvements. Specifically, the CDLD method can be used as an enhanced Stubline decoupling, improving on its accuracy and transient response, or it can be combined with an SSN solver to improve its computational performance and remove bottleneck issues. The CDLD method was tested on three IEEE benchmark systems in a real-time environment, and significant improvement was realized in network response and computational performance compared to the prevailing methods. The combined SSN-CDLD method proved to be the most promising approach for network decoupling.

Complex Morphological Filtering For Serial, Parallel, GPU, SoC, PetaLinux And FPGA Execution

Image processing is a vast field of research and extremely important for a large number of applications such as security systems, geoprocessing, medical technologies, etc. There are some applications that require a higher level of processing, requiring higher computing power. As an example of this requirement in image processing, morphological filtering with filter chains involving erosion and dilation may be used. This study aims to discuss the advantages and disadvantages between running these chains in a software context, using a personal computer, and in a hardware context, using the ZedBoard board running these filters in baremetal, FPGA and embedded linux modes. In addition, a discussion on the possibilities of parallel hardware processing, inspired by the multi-core environment and its power, will be discussed.

An effective scheme for memory congestion reduction in multi-core environment

In modern NUMA systems, increasing number of cores lead to a heavy congestion on shared caches and memory controllers. Therefore, in this paper, we propose a method (RCLB) which is capable of reducing the memory congestion with reconcile locality of communication. It prevents the load imbalancing on memory controllers which identifies the data traffic applying through clusters using MPI communication patterns. The proposed method works at the running time of MPI application with a small modification in the profiling technique. We have tested the kernels of NAS parallel benchmarks and found it as state-of-art. The experimental results show that the proposed method has achieved a bandwidth improvement ranges 12.65–23% in memory-based tests (CLB).

Hybrid-DCA: A double asynchronous approach for stochastic dual coordinate ascent

In prior works, stochastic dual coordinate ascent (SDCA) has been parallelized in a multi-core environment where the cores communicate through shared memory, or in a multi-processor distributed memory environment where the processors communicate through message passing. In this paper, we propose a hybrid SDCA framework for multi-core clusters, the most common high performance computing environment that consists of multiple nodes each having multiple cores and its own shared memory. We distribute data across nodes where each node solves a local problem in an asynchronous parallel fashion on its cores, and then the local updates are aggregated via an asynchronous across-node update scheme. The proposed double asynchronous method converges to a global solution for L-Lipschitz continuous loss functions, and at a linear convergence rate if a smooth convex loss function is used. Extensive empirical comparison has shown that our algorithm scales better than the best known shared-memory methods and runs faster than previous distributed-memory methods. Big datasets, such as one of 280 GB from the LIBSVM repository, cannot be accommodated on a single node and hence cannot be solved by a parallel algorithm. For such a dataset, our hybrid algorithm takes less than 30 s to achieve a duality gap of 10−5 on 16 nodes each using 12 cores, which is significantly faster than the best known distributed algorithms, such as CoCoA+, that take more than 160 s on 16 nodes.

Parameter Analysis of Interfering Applications in Multi-Core Environment for Throughput Enhancement

In Multi-core systems the applications co-execute in Multi-programmed mode, have interfere with each other during execution, which creates resource bottleneck affecting the performance. To reduce the interference in a given set of resources some conventional approaches don't give guarantee of performance in a conflicting application environment. In this paper, we make an in-depth analysis of benchmark applications interference for shared resources and find out application set which could be executed adopting a designated policy to mitigate the interference effects. In this work, we have performed profiling and analysis of applications on the state-of-the-art simulator gem5. Finally, we conclude the possibility of performance improvement through the designated policy. The simulation results show the scope to have a new scheduler for performance improvement in such systems.

P-Gaussian: Provenance-Based Gaussian Distribution for Detecting Intrusion Behavior Variants Using High Efficient and Real Time Memory Databases

It is increasingly important and a big challenge to detect intrusion behavior variants in today's world. Previous host-based intrusion detection methods typically explore the sequence of system calls or unix shell commands to detect the intrusion behavior. This article abstracts the detection of intrusion behavior variants as the comparison between different sequences when the sequence order or length transforms. To overcome the impact of sequence transformation on the detection accuracy, we propose P-Gaussian, a provenance-based Gaussian distribution detection scheme which comprises two key design features: (1) it utilizes provenance to describe and identify intrusion behavior variants, and eliminates the impact of sequence order transformation on the detection accuracy. (2) it adopts Gaussian distribution principle to accurately compute the similarity between intrusion behavior and its variant, and eliminates the impact of intrusion behavior sequence length increase on the detection accuracy. To improve the detection performance, P-Gaussian employs a Redis memory database with multiple Redis instances and multiple threads to enable the parallelism of provenance processing in multi-core environments. It also classifies hot and cold provenance to provide high-efficient long-term forensic analysis. Experimental results on widely-used real world applications demonstrate the performance and efficiency of our system.

Wireless Network On-Chips History-Based Traffic Prediction for Token Flow Control and Allocation

Wireless network-on-chip (WiNoC) uses a wireless backbone on top of the traditional wired-based NoC which demonstrated high scalability. WiNoC introduces long-range single-hop link connecting distanced core and high bandwidth radio frequency interconnects that reduces multi-hop communication in conventional wired-based NoC. However, to ensure full benefits of WiNoC technology, there is a need for fair and efficient Medium Access Control (MAC) mechanism to enhance communication in the wireless Network-on-Chip. To adapt to the varying traffic demands from the applications running on a multicore environment, MAC mechanisms should dynamically adjust the transmission slots of the wireless interfaces (WIs), to ensure efficient utilization of the wireless medium in a WiNoC. This work presents a prediction model that improves MAC mechanism to predict the traffic demand of the WIs and respond accordingly by adjusting transmission slots of the WIs. This research aims to reduce token waiting time and inefficient decision making for radio hub-to-hub communication and congestion-aware routing in WiNoC to enhance end to end latency. Through system level simulation, we will show that the dynamic MAC using an History-based prediction mechanism can significantly improve the performance of a WiNoC in terms of latency and network throughput compared to the state-of-the-art dynamic MAC mechanisms.

DPTree

The emergence of persistent memory (PM) spurs on redesigns of database system components to gain full exploitation of the persistence and speed of the hardware. One crucial component studied by researchers is persistent indices. However, such studies to date are unsatisfactory in terms of the number of expensive PM writes required for crash-consistency. In this paper, we propose a new persistent index called DPTree (Differential Persistent Tree) to address this. DPTree's core idea is to batch multiple writes in DRAM persistently and later merge them into a PM component to amortize persistence overhead. DPTree includes several techniques and algorithms to achieve crash-consistency, reduce PM writes significantly, and maintain excellent read performance. To embrace multi-core processors, we present the design of concurrent DPTree. Our experiments on Intel's Optane DIMMs show that DPTree reduces PM writes by a factor of 1.7x-3x compare to state-of-the-art counterparts. Besides, DPTree has a competitive or better read performance and scales well in multi-core environment.

LMAP_S: Lightweight Multigene Alignment and Phylogeny eStimation

BackgroundRecent advances in genome sequencing technologies and the cost drop in high-throughput sequencing continue to give rise to a deluge of data available for downstream analyses. Among others, evolutionary biologists often make use of genomic data to uncover phenotypic diversity and adaptive evolution in protein-coding genes. Therefore, multiple sequence alignments (MSA) and phylogenetic trees (PT) need to be estimated with optimal results. However, the preparation of an initial dataset of multiple sequence file(s) (MSF) and the steps involved can be challenging when considering extensive amount of data. Thus, it becomes necessary the development of a tool that removes the potential source of error and automates the time-consuming steps of a typical workflow with high-throughput and optimal MSA and PT estimations.ResultsWe introduce LMAP_S (Lightweight Multigene Alignment and Phylogeny eStimation), a user-friendly command-line and interactive package, designed to handle an improved alignment and phylogeny estimation workflow: MSF preparation, MSA estimation, outlier detection, refinement, consensus, phylogeny estimation, comparison and editing, among which file and directory organization, execution, manipulation of information are automated, with minimal manual user intervention. LMAP_S was developed for the workstation multi-core environment and provides a unique advantage for processing multiple datasets. Our software, proved to be efficient throughout the workflow, including, the (unlimited) handling of more than 20 datasets.ConclusionsWe have developed a simple and versatile LMAP_S package enabling researchers to effectively estimate multiple datasets MSAs and PTs in a high-throughput fashion. LMAP_S integrates more than 25 software providing overall more than 65 algorithm choices distributed in five stages. At minimum, one FASTA file is required within a single input directory. To our knowledge, no other software combines MSA and phylogeny estimation with as many alternatives and provides means to find optimal MSAs and phylogenies. Moreover, we used a case study comparing methodologies that highlighted the usefulness of our software. LMAP_S has been developed as an open-source package, allowing its integration into more complex open-source bioinformatics pipelines. LMAP_S package is released under GPLv3 license and is freely available at https://lmap-s.sourceforge.io/.

Research on Identity Mechanism of Large-scale Drug Virtual Screening in Heterogeneous Multicore Environment and SMP Environment

This paper studies the mechanism of ultra-large-scale drug virtual screening in the heterogeneous multicore environment and SMP (Symmetric Multi-Processor) environment. Given the differences caused by different CPUs, we solved the incompatibility of the open-source molecular docking software Autodock Vina on two supercomputer systems in different environments and realized the automatic and intelligent large-scale virtual screening process for small-molecule ligands. At the same time, we propose a processing method of large-scale virtual screening using Autodock Vina in two environments, which makes full use of the dominant computing power of supercomputers to improve the efficiency of large-scale molecular docking and reduce the load of different supercomputer systems facing large-scale molecular docking tasks. Finally, we conduct a virtual screening experiment on the X86 platform supercomputer and the Sunway TaihuLight Supercomputer based on the heterogeneous multicore architecture CPU—SW26010. The experimental results show that our large-scale drug virtual screening method for different CPU environments is effective.

CNDS-Performance Analysis of Parallel Programming Models for Compute-Intensive Problems in Multi-core Environment

CNDS-Performance Analysis of Parallel Programming Models for Compute-Intensive Problems in Multi-core Environment

Concurrent Treaps and Impact of Locking Objects

We propose algorithms to perform operations concurrently on treaps in a shared memory multi-core environment. Concurrent treaps hold the advantage of using nodes’ priority for maintaining the height of the treaps. To achieve synchronization, concurrent treaps make use of fine-grained locking mechanism along with logical ordering and physical ordering of nodes’ keys. We initially study the throughput and performance-per-Watt (PPW) of our concurrent treap implementation and observe that it scales well, and performs better than the state-of-the-art implementations. We further continue studies to understand the impact of different locking objects on both throughput and PPW. Our experiments show that a concurrent treap implementation that uses AtomicInteger as the locking object provides better throughput and PPW, at the same time uses a low memory footprint. As part of the application study, we consider concurrent interval trees by choosing different underlying concurrent search tree implementations as the base. We observe that the concurrent interval tree implementation that uses concurrent treap as an underlying data structure provides better throughput.

Predicting performance in multi-core systems with shared reconfigurable accelerators

Reconfigurable multi-core architectures, where general-purpose processors are extended with reconfigurable logic, present an interesting design choice for their capacity of efficiently executing both sequential as well as parallel workloads. Current state-of-the-art implementations distinguish between dedicated accelerators (where each core has access to its own reconfigurable fabric, for maximum performance) and shared ones (where a reconfigurable fabric is shared among cores, for maximum resource utilization), but no design-time guidance is provided for choosing the best implementation. In this work, we propose a new metric to guide the design of shared reconfigurable accelerators (independent of the hardware implementation) in multi-core environments by numerically assessing their rate of concurrency. We evaluate it with an 8-core system where any given number of coarse-grained reconfigurable arrays supporting transparent acceleration (i.e. with no changes in the binary) are available to execute multi-threaded applications. Using performance simulation from gem5, we show that while poorly correlated with an application’s thread-level parallelism (TLP), the proposed metric correlates strongly with the speedup achieved when switching from a shared fabric to dedicated per-core accelerators, and therefore can aid the designer in choosing the best strategy for implementing a reconfigurable multi-core architecture.

Variational inequality‐based particle discontinuous deformation analysis

SummaryOrienting the circular and rigid particle medium, the variational inequality‐based discontinuous deformation analysis (DDA) is established. In the proposed DDA, the global stiffness matrix, the penalty parameters, and the open‐close iteration are successfully avoided. The contact constraint is transferred into the problem of variational or quasi‐variational inequalities. And explicit variational expression on the contact force is firstly established. To speed up the rate of solving contact force, on the basis of the two‐stage prediction‐correction method, we design a compatibility iteration algorithm (PPC‐CI). The C++ code is developed in multicore environment through the open multi‐processing (OpenMP) in order to take advantage of the parallelizable features of the new DDA. Numerical tests suggest that the presented DDA is effective and promising.

Multivariate Missing Data Handling with Iterative Bayesian Additive Lasso (IBAL) Multiple Imputation in Multicore Environment on Cloud

Dealing with high dimensional data of the form p>n for multivariate analysis of missingness is very complicated. It arises in many fields mainly in social science, economics and medical study; genome is an example for that where is to mention that samples are very less compared to study elements nothing but variables. The analysis is a combination of large covariate vectors with response and non-response effects of unknown functional form related to response variable of interest. Thus, there is a need for regularized regression models, with effect of smoothing parametric method to do this in this work combine regularization by incorporating different types of covariates. Although regularization approaches fits to framework but the computation high demands in high dimensional analysis they also rely on penalized estimation. The solution is to implement regularization in iteration based smoothing approaches to fit such analysis. The proposed algorithm called Iterative Bayesian Additive Lasso (IBAL) is compared with standard methods in medical analysis and produced unbiased results. The overall work done in multi core environment offered by Cloud Service called Microsoft Azure. The performance is estimated with benchmarks like Standard Error (SE), Mean Square Error (MSE), and Confidence Interval (CI).

Distributed Based Serial Regression Multiple Imputation for High Dimensional Multivariate Data in Multicore Environment of Cloud

Multiple imputations (MI) are predominantly applied in such processes that are involved in the transaction of huge chunks of missing data. Multivariate data that follow traditional statistical models undergoes great suffering for the inadequate availability of pertinent data. The field of distributed computing research faces the biggest hurdle in the form of insufficient high dimensional multivariate data. It mainly deals with the analysis of parallel input problems found in the cloud computing network in general and evaluation of high-performance computing in particular. In fact, it is a tough task to utilize parallel multiple input methods for accomplishing remarkable performance as well as allowing huge datasets achieves scale. In this regard, it is essential that a credible data system is developed and a decomposition strategy is used to partition workload in the entire process for minimum data dependence. Subsequently, a moderate synchronization and/or meager communication liability is followed for placing parallel impute methods for achieving scale as well as more processes. The present article proposes many novel applications for better efficiency. As the first step, this article suggests distributed-oriented serial regression multiple imputation for enhancing the efficiency of imputation task in high dimensional multivariate normal data. As the next step, the processes done in three diverse with parallel back ends viz. Multiple imputation that used the socket method to serve serial regression and the Fork Method to distribute work over workers, and also same work experiments in dynamic structure with a load balance mechanism. In the end, the set of distributed MI methods are used to experimentally analyze amplitude of imputation scores spanning across three probable scenarios in the range of 1:500. Further, the study makes an important observation that due to the efficiency of numerous imputation methods, the data is arranged proportionately in a missing range of 10% to 50%, low to high, while dealing with data between 1000 and 100,000 samples. The experiments are done in a cloud environment and demonstrate that it is possible to generate a decent speed by lessening the repetitive communication between processors.

Cache control techniques to provide QoS on real systems

In a multicore environment, the operating system often coschedules programs on different cores simultaneously to improve utilization of system resources. As a result, the programs compete with each other for the shared last level cache, resulting in cache interference and reduced performance. Providing Quality of Service or QoS guarantees for performance of applications running in such environments has been an important area of research in the past decade. We propose a system to provide such guarantees using hardware support provided in modern processors. Our system supports specifying performance targets for high-priority programs and performance constraints for low-priority programs. The system strives to meet the given performance targets while ensuring that the performance constraints are always met. While previous works have explored cache partitioning and rate-based techniques to provide QoS, we have used direct cache control support provided in modern processors. We have explored two cache control techniques—core level control and application page level control. We have carefully selected a wide variety of workloads and performed extensive experiments on real systems. We have obtained on average 95.2% accuracy, with as high as 99.4% in some cases.

Performance and Scalability of the Block Low-Rank Multifrontal Factorization on Multicore Architectures

Matrices coming from elliptic Partial Differential Equations have been shown to have a low-rank property that can be efficiently exploited in multifrontal solvers to provide a substantial reduction of their complexity. Among the possible low-rank formats, the Block Low-Rank format (BLR) is easy to use in a general purpose multifrontal solver and its potential compared to standard (full-rank) solvers has been demonstrated. Recently, new variants have been introduced and it was proved that they can further reduce the complexity but their performance has never been analyzed. In this article, we present a multithreaded BLR factorization and analyze its efficiency and scalability in shared-memory multicore environments. We identify the challenges posed by the use of BLR approximations in multifrontal solvers and put forward several algorithmic variants of the BLR factorization that overcome these challenges by improving its efficiency and scalability. We illustrate the performance analysis of the BLR multifrontal factorization with numerical experiments on a large set of problems coming from a variety of real-life applications.

In-memory transaction processing: efficiency and scalability considerations

Traditional disk-resident OLTP systems were mainly designed for computers with relatively small memory. Driven by the advance of hardware, OLTP systems need to be redesigned for larger memory and multi-core environments. Compared to disk-resident systems, in-memory systems have significant performance advantages, from the perspectives of both transaction throughput and query latency. Their performance is no longer limited by disk I/Os. Instead, the efficiency and scalability over multi-core CPUs become more important. In this paper, we survey and summarize a wide spectrum of design and implementation considerations that may affect the efficiency or scalability of an in-memory OLTP system. These considerations are concerned with most of the main components of databases, including concurrency control, logging, indexing and transaction compilation. For each of the components, we provide some in-depth analysis based on recent research works. This survey also aims to provide some guidance for designing or implementing high-performance in-memory OLTP systems.

Accelerating Synchronization Using Moving Compute to Data Model at 1,000-core Multicore Scale

Thread synchronization using shared memory hardware cache coherence paradigm is prevalent in multicore processors. However, as the number of cores increase on a chip, cache line ping-pong prevents performance scaling for algorithms that deploy fine-grain synchronization. This article proposes an in-hardware moving computation to data model (MC) that pins shared data at dedicated cores. The critical code sections are serialized and executed at these cores in a spatial setting to enable data locality optimizations. In-hardware messages enable non-blocking and blocking communication between cores, without involving the cache coherence protocol. The in-hardware MC model is implemented on Tilera Tile-Gx72 multicore platform to evaluate 8- to 64-core count scale. A simulated RISC-V multicore environment is built to further evaluate the performance scaling advantages of the MC model at 1,024-cores scale. The evaluation using graph and machine-learning benchmarks illustrates that atomic instructions based synchronization scales up to 512 cores, and the MC model at the same core count outperforms by 27% in completion time and 39% in dynamic energy consumption.