Demand for increased data rates in serial link transceivers calls for innovative architectures capable of overcoming impairments such as limited channel bandwidth (BW) and stringent jitter specifications. This article presents a receiver front-end (RXFE) architecture that supports multicarrier signaling to provide a ~3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> relaxation in clock jitter requirements. A total of 40 Gb/s data rate is supported by three 4-GS/s bands with baseband (BB) four-level pulse amplitude modulation (PAM4) and mid-band (MB) and high-band (HB) 16-state quadrature amplitude modulation (QAM16) on 4- and 8-GHz orthogonal carriers, respectively. The RXFE uses three per-band optimized continuous-time linear equalizers (CTLEs) to partially equalize the in-band channel loss and four-way time-interleaved 7-b pipelined-successive approximation register (SAR) analog-to-digital converters (ADCs). Tight band spacing is achieved with tolerable inter-channel interference (ICI) using resettable integrators in the receiver segments. Fabricated in a 22-nm fin field-effect transistor (FinFET), the proposed 40-Gb/s multicarrier RXFE can tolerate up to 1.6-psrms jitter and achieve a bit error rate (BER) < 10−5 operating over a channel with 20-dB loss at 10 GHz when combined with an off-chip one-tap digital ICI canceller. The ADC-based front-end achieves 3.05-pJ/bit power efficiency, including all the front-ends, ADC, and clocking power.