Multiple-valued Logic Research Articles

Improving the efficiency of using multivalued logic tools

Multivalued logics are becoming one of the most important tools of information technology. They are in great demand for creation of artificial intelligence systems that are close to human intelligence, since the functioning of the latter cannot be reduced to the operations of binary logic. At the same time, the problem of improving the efficiency of using the results of research in multivalued logics, as well as the problem of interpreting variables of multivalued logic, is acute. These problems create certain interdisciplinary barriers and make it difficult to implement the results of research in the field of multivalued logics in other fields of knowledge. It is shown that the problem of interpreting multivalued logic variables can be removed by establishing correspondence with fuzzy logic variables. Improving the efficiency of using of operations of multivalued logics and their variables can be provided by using their close connection to Galois fields. This connection, among other things, makes it possible to reduce any operations of multivalued logics, the number of variables in which is equal to a prime number, to algebraic functions whose arguments take values in Galois fields. This allows, among other things, to eliminate the very cumbersome constructions used in works on multivalued logic and make its apparatus convenient for use in related scientific disciplines in information technology. Direct verification of the adequacy of algorithms based on the use of Galois fields can be carried out by means of radio-electronic circuits, examples of which are presented in the present paper.

Performance analysis of 4-bit ternary adder and multiplier using CNTFET for high speed arithmetic circuits

Multiple valued logic (MVL) can represent an exponentially higher number of data/information compared to the binary logic for the same number of logic bits. Compared to the conventional devices, the emerging device technologies such as Graphene Nano Ribbon Field Effect Transistor (GNRFET) and carbon nanotube field effect transistor (CNTFET) appears to be very promising for designing MVL logic gates and arithmetic circuits due to some exceptional electrical properties such as the ability to control the threshold voltage. This variation of the threshold voltage is one of the prescribed techniques to achieve multiple voltage levels to implement the MVL circuit.This work presents a 4-input ternary adder using carbon nanotube field effect transistor (CNTFET). Many researchers have been done work on implementation of ternary adders and multipliers. But no one has done the comparison of this proposed ternary adder with different types of nano transistors. Hence this work has been proposed a design of low power and high speed 4-input adder which will be useful for designing of fast ternary multipliers. All the proposed designs have been simulated using emerging device such as CNTFET at 32nm technology node. From the simulations, we have calculated the power consumptions of the proposed designs, carry propagation delay and power delay product for the CNTFET circuits. It has been observed that CNTFET based proposed logic circuits given a better performance than the conventional logical circuits.

О неявных расширениях в многозначной логике

Рассматривается неявная выразимость А. В Кузнецова и ее обобщения, когда в язык неявной выразимости вносятся дополнительные логические связки: дизъюнкция, импликация и отрицание. Установлено, что при любом $k\geqslant 3$ число неявных расширений в $P_k$ континуально. Доказано, что при $k\geqslant 3$ каждое из множеств позитивно неявных, импликативно неявных и негативно неявных расширений в $P_k$ собственным образом содержит соответственно множество позитивно неявных, импликативно неявных и негативно неявных замкнутых классов. Установлено, что при $k\geqslant 2$ при получении импликативно неявных и негативно неявных расширений без изменения результата можно использовать функции множества $H_k^*$ однородных функций, сохраняющих множество $E_{k-1}$.

Re-Establishing a Lost Connection: Multi-Value Logic in Causal Data Analysis in Social Science Disciplines

The main purpose of logic optimization lies in architecting integrated switching circuits. It is thus a topic well covered in electrical engineering. Some subfields of the social sciences have also employed algorithms for logic optimization since the mid-1980s to infer about cause-effect relations. Most notably, political scientists and sociologists have developed Qualitative Comparative Analysis (QCA), a configurational comparative method (CCM) that relies on the well-known Quine-McCluskey algorithm. However, while electrical engineering has progressed considerably since the advent of logic optimization in the 1950s, these advancements have not been monitored by social scientists. Nor have social scientists sought to establish interdisciplinary collaboration. The objective of our article is twofold. First, and more generally, we seek to build a bridge between electrical engineering and configurational causal inference. Secondly, and more specifically, we present Combinational Regularity Analysis (CORA), a new CCM that has been inspired by electrical engineering. In particular, we introduce one of CORA’s algorithms for optimizing highly unspecified multi-value logic functions with multiple outputs. The availability of such algorithms in CORA pushes the boundaries of configurational causal inference and attests to the extent to which configurational comparative methodology could benefit from more interdisciplinary collaboration with electrical engineering.

Метод синтезу s-блоків на основі матриць gf-перетворення

Cryptographic methods today are a crucial tool for constructing information security systems. At the same time, to solve the problem of encrypting large amounts of information, block or stream symmetric ciphers are mainly preferred because of their efficiency and proven cryptographic strength, including against perspective quantum cryptanalysis. The effectiveness of modern symmetric ciphers largely depends on the cryptographic S-boxes applied in their construction, the quality of which largely determines the degree of implementation of the concepts of diffusion and confusion by the cryptographic algorithm, while the presence of large sets of cryptographically high-quality S-boxes is also important, in the terms of their application as a long-term key. Today, the Nyberg construction is well-known and widely applied in ciphers, including widespread AES block symmetric cipher. This construction allows you to synthesize high-quality S-boxes that harmoniously satisfy the main criteria for cryptographic quality, however, the set of S-boxes synthesized using this construction is small, which makes the task of developing new methods for synthesizing large sets of cryptographically high-quality S-boxes highly relevant. At the same time, as research shows, the constructions of extended Galois fields are a promising raw material for solving this problem. In this paper, the Galois field transform matrices of order N=256 are constructed for all isomorphic representations of the extended Galois field GF(256) which are analogous to the Reed-Muller transform but for the case of many-valued logic functions. As part of the research, the isomorphism invariant row numbers of the Galois field transform matrices are identified, which allows to obtain bijective S-boxes, as well as bijective S-boxes that correspond to the main criteria for cryptographic quality of component Boolean functions such as algebraic degree of nonlinearity, distance of nonlinearity, error propagation criterion, and criterion of minimization of correlation of output and input vectors of the S-box. At the same time, the cardinality of the set of synthesized S-boxes is ~23 times higher than the cardinality of the set of S-boxes of the Nyberg construction, which allows them to be used as a long-term key. The proposed S-boxes can become the basis for improving the effectiveness of existing symmetric cryptographic algorithms and developing new ciphers.

Critical Rationalism and Bayesianism

Most accounts of the scientific method, e.g.s the Deductive-Nomological (D-N), Inductive Statistical (I-S), and so on, attempt to avoid Hume’s problem. Popper’s philosophy of critical rationalism and subjectivist Bayesianism come into conflict here on a number of points. The most noteworthy is on the problem of induction. That is, if science rests on induction (as Sir Francis Bacon would have it), and induction cannot be justified according to the strict demands of classical deductive validity without invoking a circularity, how can we say that science is rational? And how should scientists proceed? Bayesians utilizes a consistent multivalued logic that adheres to the Kolmogorov axioms. And on the other side, Sir Karl Popper maintains that the real logic of science is deductive. It is a myth that induction is even used. I will evaluate both claims through a third-party lens. That is, Micheal Ruse’ s epigenetic account of inferential reasoning. This is a modified version of Hume’s propensity theory. Ultimately, deductivism cannot explain how proto-humans behaved in the wild. How they grew smarter, became tool-using beings, and became the dominant species on the planet.

Monolithic Tandem Vertical Electrochemical Transistors for Printed Multi-Valued Logic.

Organic electrochemical transistors (OECTs) have recently emerged as a feasible candidate to realize the next generation of printable electronics. Especially, their chemical versatility and the unique redox-based operating principle have provided new possibilities in high-functioning logic circuitry beyond the traditional binary Boolean logic. Here, a simple strategy to electrochemically realize monolithic multi-valued logic transistors is presented, which is one of the most promising branches of transistor technology in the forthcoming era of hyper Moore's law. A vertically stacked heterogeneous dual-channel architecture is introduced with a patterned reference electrode, which enables a facile manifestation of stable and equiprobable ternary logic states with a reduced transistor footprint. The dual-ion-penetration mechanism coupled with ultrashort vertical channel even allows a very-high accessing frequency to multiple logic states reaching over 10MHz. Furthermore, printed arrays of ternary logic gates with full voltage swing within 1V are demonstrated.

МАТЕМАТИЧНИЙ ОПИС ОПЕРАЦІЇ ДИФЕРЕНЦІЮВАННЯ В ЛОГІКО-ЧАСОВОМУ СЕРЕДОВИЩІ

Effective and timely processing of information is one of the most important problems of creating means of its processing at the level of human perception and thinking. Analytical processing of digital signals in a graphical or purely digital representation is somewhat limited and does not take into account the dynamics of signals and messages. The classical apparatus of logic is insufficient to describe the dynamics of system behavior over time. Therefore, it is important to develop models of so-called Boolean differential calculus, as this approach is based on the general concept of changing the logical variable, which will lead to a universal, in terms of dynamics, system of concepts and operations. To facilitate the preprocessing of dynamic digital variables and signals, the logic-time function of multivalued logic can be used. The purpose of this article is a mathematical representation of the differentiation of logic-time functions of multi-valued logic in the index form of the record using the simulation of its scheme. The paper shows the expediency of the idea of replacing an arbitrary digital signal (variable) that changes over time with a logic-time function, which allows to facilitate the preliminary analytical processing of digital signals and variables using the properties of such functions. The article presents a new mathematical apparatus for describing logic-time functions of multivalued logic and individual operations on them using modeling of known implementation schemes. The paper considers the peculiarities of the derivative of the multivalued logical-time function (LMF), as one of the most used and basic operations used in the study of signals and images. Its characteristics and features are shown for functions presented in index form. The general expression of the derivative of the n order is obtained and it is shown that different logic-time functions can have the same derivative. The concepts of the left and right derivative of the LMF are introduced and the relationship between them is shown. The properties of the k derivative of the BLMF were considered and the expressions for the derivative conjunction and disjunction were obtained. A possible structural scheme of the differentiator is presented, which opens up the possibility of hardware processing of multi-valued LMFs.

Matrix elements MAX and MIN based on functions of the two-valued logic

Two-valued logic functions are proposed that are applicable as mathematical models of the MAX and MIN elements It have got a regular matrix structure, provide parallel processing of m l 2 n-bit binary variables and can be used in various automated systems as high-performance basic elements of single-chip means for logical processing of the multi-value data. The circuit implementation of the proposed mathematical models is considered. Keywords two-valued logic functions, regular structures, multi-valued logic elements

Applications of Multivalued Logic to Set Theory and Calculus

Applications of Multivalued Logic to Set Theory and Calculus

Energy Efficient Circuit Design of Single Edge Triggered Ternary Shift Registers Using CNT Technology

With the miniaturization of digital integrated circuits, electronic systems with increased functionality and enhanced performance are preferred. Multi-valued logic design is a promising alternative that offers a higher number of data/information which leads to energy efficiency, higher information density and reduced circuit overheads in terms of interconnect complexity. Hence in this work multi-valued logic design benefits of increased computational capability and reduced interconnect complexity are being explored for the implementation of sequential elements viz. ternary shift registers. Carbon nanotube field-effect transistors(CNTFETs) unique feature of alteration of threshold voltage by variations in CNT diameter further favor its suitability to implement ternary logic designs. Here single-edge triggered ternary shift registers design methodology is presented using multiplexer based D-flip-flop cells. The design of D-flip-flops is performed using multiplexer based positive and negative latches. After this series connection of D-flip-flop is performed to construct serial input serial output and parallel input serial output registers. The parallel input serial output registers can operate in two modes of loading and shifting and three different configurations of AND-OR logic, NAND logic and latch based selection circuitry are proposed. For performance analysis Synopsis HSPICE simulations are conducted using the 32nm CNTFET Stanford model. According to simulation results, for the proposed ternary shift registers maximum reduction in power consumption and energy consumption of more than 80% are obtained as compared to recent counterparts.

Graphene Bridge Heterostructure Devices for Negative Differential Transconductance Circuit Applications

HighlightsGraphene (Gr)-bridge heterostructure, consisting of a laterally series-connected (cascade) ambipolar/Gr/n-type 2D van der Waals channel materials for ambipolar semiconductor-based high-end application devices was developed.Non-classical transfer characteristics (humped curve) in FET operation and negative differential transconductances were observed.Gr-bridge heterostructure device with PdSe2 (narrow bandgap) allows multi-value logic operation while WSe2 (wide bandgap) enables frequency tripler circuit operation.

DESIGN AND SYNTHESIS OF TERNARY LOGIC ELEMENTS

The aim of this paper is creating some ternary elements. The threshold element of ternary logic on bipolar transistors and elements of ternary systems based on it are considered. The main disadvantages of this approach are identified. The multi-threshold element of multivalued logic and its specific four-threshold implementation are considered. The scientific nowelty is the using of a multithreshold element of multivalued logic as a basis for constructing elements of ternary systems. It is shown that the advantages of a multi-threshold element of multi-valued logic are a larger number of thresholds of input signals, a larger number of levels that it can distinguish and a larger number of output signals. The implementation of some ternary elements, such as half-adder, disjunction and strong conjunction, is given. The practical significance of obtained results is that the multithreshold element of multivalued logic allows us to use it for synthesis basic elements of ternary logic and use one approach for all of them. Additional practical advantage is that in practice it allows you to build more diverse logical and arithmetic devices with a simplified implementation. The implementation of ternary devices based on threshold logic is a way to create ternary devices that can compete with binary devices in terms of equipment, capacity, operational capabilities, and variety. This, in turn, leads to greater speed and simplification of the structure of devices, as well as increasing the speed of data processing. These advantages are significant in such areas of computer use as intelligent data processing systems, expert systems, decision theory, i.e., where data analysis is performed. Prospects for further research are to use the method of construction and synthesis of nodes of ternary computer systems, based on MTEML. Their optimization, and development of principles of mathematical modeling and software of such systems and their elements is expedient.

Application of the Methodology of Multi-Valued Logic Trees with Weighting Factors in the Optimization of a Proportional Valve

Hydraulic valves are used to determine the set values of hydraulic quantities (flow rate, pressure, or pressure difference) in a hydraulic system or its part. This is achieved through the appropriate throttling of the stream flowing through the valve, which is automatically set by the operator (e.g., opening the throttle valve). The procedures for determining its static and dynamic properties were described using the example of modeling a two-stage proportional relief valve. Subsequently, the importance of the design and operational parameters was determined using multi-valued logic trees. Modeling began with the determination of equations describing the flow and movement of moving parts in a valve. Based on the equations, a numerical model was then created, e.g., in the Matlab/Simulink environment (R2020b). The static characteristics were obtained as the result of a model analysis of slow changes in the flow rate through the valve. Various coefficients of logical products have not been taken into account in the separable and common minimization processes of multi-valued logic equation systems in any available literature. The results of the model tests can be used to optimize several types of hydraulic valve constructions.

Enhanced algorithmic modelling and architecture in deep reinforcement learning based on wireless communication Fintech technology

Financial technology” or “FinTech” refers to use of information technologies to derive financial solutions. FinTech is now widely regarded as a hotly debated blend of financial services and information technology. A combination of AI and IoT approaches will significantly increase the extraction of valuable financial data as well as provide better services to customers. This research proposed a novel protocol in data transmission using fuzzy rule-based secure transmission with data optimization technique using deep reinforcement neural network by wireless communication. This technique for data transmission will reduce the credit risk and enhances the data optimization by fuzzy rule-based protocol with DRNN. The logic utilized is fuzzy logic, which is a multi-valued logic with truth values for variables ranging from 0 to 1. When truth values range from entirely true to completely false, it is used. The end user's searching experience is improved by fuzzy logic-based semantic search, which finds and retrieves exact matching files for relevant search files provided by user. When exact matches aren't possible, method leverages semantic similarities to determine most relevant matches. A grading method is utilized to minimize number of false positives. For this, proposed technique was used, which may decide on a collection of suitable storage servers on which the data must be saved and resulting in a reduction in execution time while maintaining a higher level of security. The experimental results show the execution time of 54 %, network performance of 96 %, the overall complexity of 71 %, data optimization of 95 % and end-end delay of 67 %.

Using multivalued logic for qualitative data analysis

В статье рассматривается логический подход к анализу данных для решения задачи классификации. Исследуемые данные представляют собой совокупность объектов и их признаков. Как правило, это разрозненная разнородная информация, и ее недостаточно для разумного применения вероятностных моделей. Поэтому рассматриваются логические алгоритмы, которые при определенных условиях могут оказаться более адекватными. Для выразительного формального представления отношений между объектами и их атрибутами используется многозначная логика, а количество значений зависит от конкретного атрибута. Поэтому предлагается система операций над переменными с разными областями определения. В результате строится решающая функция, которая является классификатором объектов, присутствующих в изучаемых данных. Анализируются свойства и возможности этой функции. Показано, что логическая функция, являющаяся конъюнкцией в пространстве правил, связывающих заданные объекты с их характерными признаками, однозначно характеризует исходные данные, делит предметную область на классы, обладает свойствами модифицируемости, удовлетворяет требованиям полноты и непротиворечивости в заданная область. В работе также предлагается алгоритм его реализации The article considers a logical approach to data analysis for solving the classification problem. The studied data is a set of objects and their features. As a rule, this is disparate heterogeneous information, and it is not enough for a reasonable application of probabilistic models. Therefore, logical algorithms are considered, which, under certain conditions, may be more adequate. For an expressive formal representation of the relationship between objects and their attributes, multivalued logic is used, and the number of values depends on the particular attribute. Therefore, a system of operations on variables with different domains is proposed. As a result, a decision function is built, which is a classifier of objects present in the studied data. The properties and possibilities of this function are analyzed. It is shown that a logical function, which is a conjunction in the space of rules that connect given objects with their characteristic features, unambiguously characterizes the initial data, divides the subject area into classes, has modifiability properties, satisfies the requirements of completeness and consistency in the given area. The paper also proposes an algorithm for its implementation.

Step-like current–voltage thin-film transistors with amorphous SiZnSnO/SiInZnO/SiZnSnO multilayered-channels

• Observation of step-like transfer curves (I-V) • The organic barrier layer is replaced by inorganic (SIZO) material in this work. • Only amorphous semiconductors (inorganic materials) were used to obtain the step-like behaviour in the IV characteristics. • This study will be beneficial for the recent application of multi-value logic (MVL) circuits. Multi-valued logic (MVL) is a critical approach for high-density information and next-generation digital electronics. Recently developed multilayered-channel structure electronic devices provide new transistor operation of multi-valued logic switching characteristics. This paper investigates the step-like transfer curves of the amorphous SiZnSnO/SiInZnO/SiZnSnO (a-SZTO/SIZO/SZTO or a-SSS) multilayered-channel thin-film transistors (TFTs). The step-like transfer curves of a-SSS TFTs can be tuned intentionally by varying the thickness of the top and bottom layers of a-SZTO mainly because a low conducting material is introduced as a barrier layer to separate the top and bottom layers to obtain the intermediate states. Additionally, the conducting nature of the middle/barrier layer of a-SIZO was varied and studied for different Si concentrations.

Šare’s algebraic systems

We study algebraic systems MΓ of free semigroup structure, where Γ is a well ordered finite alphabet, discovered in 1970s within the Theory of Electric Circuits by Miro Šare, and and finding recent recent applications in Multivalued Logic, as well as in Computational Linguistics. We provide three simple axioms (reversion axiom (5) and two compression axioms (6) and (7)), which generate the corresponding equivalence relation between words. We also introduce a class of incompressible words, as well as the quotient Šare system MΓ~. The main result is contained in Theorem 16, announced by Šare without proof, which characterizes the equivalence of two words by means of Šare sums. The proof is constructive. We describe an algorithm for compression of words, study homomorphisms between quotient Šare systems for various alphabets Γ (Theorem 38), and introduce two natural Šare categories ŠŠa(M) and ŠŠa(M~). Šare systems are not inverse semigroups.

Об истоках множественности логик

The article presents a brief analysis of how the existence of various logics became possi­ble. This is shown on the example of such well-known logical theories as syllogistics, temporal, multivalued, intuitionistic, paraconsistent and quantum logics. Each of them arose not on someone’s whim, but to solve specific problems. They are based on the most general ontological assumptions about the subject area under study. In formal logic onto­logical assumptions are refined in the concept of a model structure. Since it is impossible to talk about logic in isolation from the language used, the most general epistemic as­sumptions about the nature of the relationship of linguistic expressions to those objects of extralinguistic reality that they represent are also accepted. One of the most important of these relationships is the concept of the truth of sentences, which was first formulated by Plato and Aristotle. Taking certain ontological and epistemic assumptions depending on the problem being solved, we obtain different logics. Process logic is primarily char­acterized by special ontological assumptions that are fundamentally different from the as­sumptions of other currently existing logics. The ontology of processes is an ontology of developing processes, not things. Historically, it was most vividly described in the writings of Heraclitus. In the overwhelming majority of modern approaches to the de­scription of processes, we see attempts to reduce them to sequences of states, which de­values the very concept of a process, just as a cinematic picture of the flow of time deval­ues the concept of time. Since logics are built on the basis of various ontological and epistemic assumptions, they are inherently theories of these accepted assumptions, and not universal reasoning tools that don’t depend on the characteristics of the study area and the categories of linguistic expressions. Universal logic is possible if one rises from the level of specific languages to a higher level of sign theory.

DESIGN OF LOW POWER HIGH SPEED CNTFET ADDER SUBTRACTOR

Multi-valued logic design itself is not sufficient to achieve the performance improvement in digital system design in nanotechnology. The need to replace silicon devices with some more efficient new devices are required so as to meet the power improvements in the nanoscale region. Among various devices explored, CNTFET is the most promising alternative to replace conventional MOS transistors. These nano devices have the benefits of low power consumption due to reduced leakage component, ballistic transport operation even at low supply voltages makes them suitable for high frequency and low voltage applications. MVL circuitry has soared in popularity because the threshold voltage of the CNFET device is somewhat adjustable by the diameter of carbon nanotubes. CNFET is used for high performance, high stability and low-power circuit designs as an alternative material to silicon in recent years. Carbon Nanotube Filed-Effect Transistor (CNFET) is one of the promising alternatives to the MOS transistors. The geometry- dependent threshold voltage is one of the CNFET characteristics, which is used in the proposed design. In this paper, we present a novel high speed Adder-subtractor cell using CNFETs based on XOR gates and multiplexer. Proposed design uses fourteen transistors, ten for full adder and four to modify the cell for subtraction. Simulation results show significant improvement in terms of delay and area saving with respectively compared to the latest design. Simulations were carried out using HSPICE based on CNFET model with optimized design parameters. All designs are simulated at 32nm CNFET with HSPICE. The simulation results show that on average, speed enhancement and area saving of 48% and 11% can be achieved with optimized parameters design over default values of these parameters. The cumulative benefits of the novel adder-subtractor design based CNFET result in an PDP reduction by a factor of 41%.