Multi-threshold CMOS Circuit Research Articles

Design Techniques for Power-Gated Nanoscale Low Power Circuits

Background: With the shrinking device-sizes in the present day world, the leakage power of the devices has also been increased significantly. Several techniques have been proposed to minimize the leakage power. However, the techniques have certain limitations, such as noise, delay or area of the chip. We have also proposed a leakage minimization technique which also minimizes the noise in the circuit. Objective: In this paper, we propose noise minimization circuit techniques for the distributed sleep transistor network in power-gated Multi-threshold CMOS circuits. The objective is to minimize leakage power as well as the noise associated with digital power-gated circuits. Methods: The proposed technique has been verified through simulations using the Cadence virtuoso tool. The proposed technique has been applied to a 16-bit adder circuit in 45 nm MTCMOS technology. Results: The proposed techniques i.e. HVT-ST and the Hybrid-ST techniques achieve 99%, 64.8% and 62.07% reduction in noise as compared to the All-ON, variable-width and variable gate-voltage techniques, respectively. The behavior of the circuit techniques has also been analyzed at higher temperatures. It has been shown through simulations that the proposed techniques effectively minimize noise at higher temperatures i.e. 75°C and 115°C. The proposed techniques also minimize leakage power and the on-time delay significantly. A layout of the section of the proposed circuit has also been drawn which occupies the chip area of 2.37 µm2. Conclusion: The proposed techniques i.e. HVT-ST and the Hybrid-ST techniques achieve a significant reduction in the noise as well as delay. In this paper, we propose leakage minimization techniques for the distributed sleep transistor network. The proposed techniques i.e. HVT-ST and the Hybrid-ST techniques achieve a significant reduction in noise as well as delay. The technique also reduces the leakage power significantly.

Novel design techniques for noise-tolerant power-gated CMOS circuits

In this paper we have investigated the single phase sleep signal modulation technique, step-wise technique and the three-phase reactivation technique to evaluate the noise characteristics of multi-threshold CMOS circuits used in communication systems. The stacking technique is also implemented in this paper for the sleep transistor. The stacking approach helps to minimize leakage power. The mode transition noise minimization techniques have been applied to 32-bit dynamic TSPC adder with stacked sleep transistors in a standard 45-nm CMOS process. The reactivation noise, delay and energy consumption of all the three techniques have been evaluated. It has been shown that the three phase modulation technique significantly minimizes the reactivation delay when the peak noise level is maintained the same for all three techniques. The three phase modulation technique shows 67.3% and 35% reduction in delay compared to the single phase and step-wise modulation techniques respectively. The reactivation energy is also suppressed by 49.3% and 39.14% with respect to the single-phase and stepwise techniques.

Mode transition timing and energy overhead analysis in noise-aware MTCMOS circuits

Multi-threshold CMOS (MTCMOS) is commonly utilized for suppressing leakage currents in idle integrated circuits. The deactivation/reactivation energy consumption however degrades the effectiveness of the MTCMOS technique for providing significant savings in total energy consumption in CMOS integrated circuits. The sources of mode transition energy consumption in noise-aware MTCMOS circuits are investigated in this paper. The mode transition energy overheads of various recently published low-noise ground-gated MTCMOS circuits are characterized. With a digital triple-phase sleep signal slew rate modulated MTCMOS circuit, the overall mode transition energy consumption is reduced by up to 45.31% as compared to the other MTCMOS circuits that are evaluated in this paper in a UMC 80nm CMOS technology. Furthermore, digital triple-phase sleep signal slew rate modulation shortens the mode transition timing overhead by up to 65.26% as compared with the other MTCMOS noise suppression techniques that are evaluated in this paper.

Ground bounce noise reduction aware combinational multi threshold CMOS circuits for nanoscale CMOS multiplier

Multi-threshold complementary metal-oxide-semiconductor (MTCMOS) is often used to reduce the leakage current in idle circuit. Ground bounce noise produced during a transition mode (sleep-to-active) is an important challenge in MTCMOS. In this paper, various noise-aware combinational MTCMOS circuit was used to evaluate the ground bounce noise. An intermediate mode was applied in the sleep-to-active mode transition to reduce the charge stored on virtual lines to real ground. The dependence of ground bounce noise on voltage, transistor size and temperature was investigated with different MTCMOS circuit technique. The peak amplitude of ground bounce noise was reduced up to 78.82%. The leakage current of the circuit was decreased up to 99.73% and the active power of the circuit was reduced up to 62.32%. Simulation of multiplier with different MTCMOS circuit techniques was performed on 45 nm CMOS technology.

Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS Circuits

Multi-threshold CMOS (MTCMOS) is commonly used for suppressing leakage currents in idle integrated circuits. Power and ground distribution network noise produced during SLEEP to ACTIVE mode transitions is an important reliability concern in MTCMOS circuits. Sleep signal slew rate modulation techniques for suppressing mode-transition noise are explored in this paper. A triple-phase sleep signal slew rate modulation (TPS) technique with a novel digital sleep signal generator is proposed. Reactivation time, mode-transition energy consumption, leakage power consumption, and layout area of different MTCMOS circuits are characterized under an equal-noise constraint. Influences of within-die and die-to-die parameter variations on the reactivation noise, time, and energy consumption of sleep signal slew rate modulated MTCMOS circuits are evaluated with a process imperfections aware robustness metric. The proposed triple-phase sleep signal slew rate modulation technique enhances the tolerance to process parameter fluctuations by up to <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$183.1\times$</tex></formula> as compared to various alternative MTCMOS noise suppression techniques in a UMC 80-nm CMOS technology.

Threshold Voltage Tuning for Faster Activation With Lower Noise in Tri-Mode MTCMOS Circuits

A new threshold voltage tuning methodology is explored in this paper to minimize the peak power/ground bouncing noise with smaller sleep transistors in multi-threshold CMOS (MTCMOS) circuits. Different circuit techniques with the threshold voltage tuning strategy lower the activation noise, the activation delay, and the size of the additional sleep transistors by up to 27.76%, 32.66%, and 85.71%, respectively, as compared to a previously published noise-aware MTCMOS circuit with standard zero-body-biased high threshold voltage sleep transistors in a UMC 80-nm CMOS technology.

Ground bouncing noise reduction technique considering wake-up delay in MTCMOS circuits

Multi-Threshold CMOS (MTCMOS) is an effective technique for controlling leakage power with low delay overhead. However the large magnitude of ground bouncing noise induced by the sleep to active mode transition may cause signal integrity problem in MTCMOS circuits. We propose a methodology for reducing ground bouncing noise under the wake-up delay constraint. An improved two-stage parallel power gating structure that can suppress the ground bouncing noise through turn on sets of sleep transistors consecutively is proposed. The size of each sleep transistor is optimized by a novel sizing algorithm based on a simple discharging model. Simulation results show that the proposed techniques achieve at least 23% improvement in the product of the peak amplitude of ground bouncing noise and the wake-up time when compared with other existing techniques.

Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits

Ground distribution network noise produced during sleep-to-active mode transitions is an important reliability concern in standard multi-threshold CMOS (MTCMOS) circuits. Different noise-aware sequential MTCMOS circuits are explored in this paper. A low-leakage data retention sleep mode is implemented with smaller centralized sleep transistors to suppress the ground bouncing noise produced during reactivation events in sequential MTCMOS circuits. Ground bouncing noise, leakage power consumption, data stability, and area overheads of different sequential MTCMOS circuits are evaluated with a 90-nm CMOS technology. The peak amplitude of ground bouncing noise is reduced by up to 94.16% with the noise-aware MTCMOS techniques as compared to the conventional Mutoh flip-flop. The application space of different data retention MTCMOS circuit techniques is identified with various design metrics in this paper.

Ground-Bouncing-Noise-Aware Combinational MTCMOS Circuits

Ground bouncing noise produced during the SLEEP to ACTIVE mode transitions is an important challenge in standard multithreshold CMOS (MTCMOS) circuits. The effectiveness of different noise-aware combinational MTCMOS circuit techniques to deal with the ground-bouncing-noise phenomenon is evaluated in this paper. An intermediate relaxation mode is investigated to gradually dump the charge stored on the virtual lines to the real ground distribution network during the SLEEP to ACTIVE mode transitions. The dependence of ground bouncing noise on the sleep transistor size and temperature is characterized with different power-gating structures. The peak amplitude of ground bouncing noise is reduced by up to 76.62% with the noise-aware techniques without sacrificing the savings in leakage power consumption as compared with standard MTCMOS circuits in a 90-nm CMOS technology.

Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits

Circuits utilizing advanced process technologies have to correctly account for device parameter variation to optimize its performance. In this paper, analytical formulas for evaluating path delay variation of Multi-Threshold CMOS (MTCMOS) circuits are proposed. The proposed formulas express path delay and its variation as functions of process parameters that are determined by fabrication technology (threshold voltage, carrier mobility, etc.) and the circuit parameters that are determined by circuit structure (equivalent load capacitance and the concurrently switching gates). Two procedures to obtain the circuit parameter sets necessary in the calculation of the proposed formulas are also defined. With the proposed formulas, calculation time of a path delay variation becomes three orders faster than that of Monte-Carlo simulation. The proposed formulas are suitably applied for efficient design of MTCMOS circuits considering process variation.

Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power

This paper presents an ultra-low power circuit design methodology which combines the Multi-Threshold CMOS (MTCMOS) technique with quasi delay-insensitive (QDI) asynchronous logic, in order to solve the three major problems of synchronous MTCMOS circuits: (1) Sleep signal generation, (2) storage element data loss during sleep mode, and (3) sleep transistor sizing. In contrast to most power reduction methods that result in area overhead, the QDI asynchronous MTCMOS circuits are usually smaller than their original versions. Moreover, QDI circuits utilize handshaking protocols instead of clocks for circuit control, resulting in flexible timing requirements, which yields increased circuit robustness and allows for extreme supply voltage scaling to subthreshold region for further power reduction, without requiring any circuit modifications. This QDI asynchronous MTCMOS methodology is used to design a 4-stage pipelined 8-bit x 8-bit unsigned multiplier, which is then compared against the original QDI design (i.e., without incorporating MTCMOS) and its synchronous version. All designs use the IBM 8RF-DM 0.13 μm process. Results show 150x and 1.8x leakage power and active energy reductions on average in the QDI asynchronous MTCMOS design compared to the original QDI version, respectively.

A functionality-directed clustering technique for low-power MTCMOS design—computation of simultaneously discharging current

Multithreshold CMOS (MTCMOS) is a circuit style that can effectively reduce leakage power consumption. Sleep transistor sizing is the key issue when a MTCMOS circuit is designed. If the size of sleep transistor is large enough, the circuit performance can surely be maintained but the area and dynamic power consumption of the sleep transistor may increase. On the other hand, if the sleep transistor size is too small, there will be significant performance degradation because of the increased resistance to ground. Previous approaches [Kao et al. 1998; Anis et al. 2002] to designing sleep transistor size are based mainly on mutually-exclusive discharge patterns. However, these approaches considered only the topology of a circuit (i.e., interconnections of nodes in the circuit-graph saving the functionality of node). We observed that any two possible simultaneously switching gates may not discharge at the same time in terms of functionality. Thus, we propose an algorithm to determine how to cluster cells to share sleep transistors, while taking both topology and functionality into consideration. Moreover, one placement refinement algorithm that takes clustering information into account will be presented. At the logic level, the results show that the proposed clustering method can achieve an average of 22% reduction in terms of the number of unit-size sleep transistors as compared to a method that does not consider functionality. At the physical level, two placement results are discussed. The first is produced by a traditional placement tool plus topology check (functionality check) for insertion of sleep transistors. It shows that the functionality check algorithm produces 9% less chip area as compared with the topology check algorithm. The second result is produced by a placement refinement algorithm where the initial placement is done in the first placement experiment. It shows that the placement refinement algorithm achieves 5% more reduction in area at the expense of 4% increase in wire length. Totally, around 14% reduction is achieved by utilizing the clustering information.

Modeling leakage power reduction in VLSI as optimization problems

Reducing power dissipation is one of the most important issues in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power dissipation. Multi-Threshold CMOS (MTCMOS) technology has emerged as a promising technique to reduce leakage power. This paper first introduces how to model the sleep transistor sizing problem in the MTCMOS circuits as a Bin-Packing Problem (BPP). The gate-clustering BPP and the First-Fit (FF) techniques are also introduced to further improve the solution quality. To take the circuit’s routing complexity into consideration which is critical for Deep Sub-Micron (technologies that are 0.25 μm and below) (DSM) implementations, a Set-Partitioning Problem (SPP) is then formed. However, this highly constrained model limits it’s application for large circuit design. A Set-Covering (SCP) model is therefore investigated to efficiently solve the problem.

Design and optimization of multithreshold cmos (mtcmos) circuits

Reducing power dissipation is one of the most important issues in very large scale integration design today. Scaling causes subthreshold leakage currents to become a large component of total power dissipation. Multithreshold technology has emerged as a promising technique to reduce leakage power. This paper presents several heuristic techniques for efficient gate clustering in multithreshold CMOS circuits by modeling the problem via bin-packing (BP) and set-partitioning (SP) techniques. The SP technique takes the circuit's routing complexity into consideration which is critical for deep submicron (DSM) implementations. By applying the techniques to six benchmarks to verify functionality, results obtained indicate that our proposed techniques can achieve on average 84% savings for leakage power and 12% savings for dynamic power. Furthermore, four hybrid clustering techniques that combine the BP and SP techniques to produce a more efficient solution are also devised. Ground bounce was also taken as a design parameter in the optimization problem. While accounting for noise, the proposed hybrid solution achieves on average 9% savings for dynamic power and 72% savings for leakage power dissipation at sufficient speeds and adequate noise margins.