Multi-stAge Noise SHaping Digital Delta-sigma Research Articles

Optimized MASH-SR Divider Controller for Fractional-N Frequency Synthesizers

The divider controller in a conventional phase-locked loop fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> frequency synthesizer modulates the instantaneous division ratio of the feedback divider. The divider controller is typically a digital circuit that performs quantization of its input signal. Multi-stage noise shaping digital delta-sigma modulators (MASH DDSMs) and successive requantizer (SRs) are two representative divider controller architectures offering lower complexity and better spur performance, respectively. The MASH-SR, as a hybrid of these two classes of divider controllers, can achieve both lower hardware cost than the SR and better performance against spurs than a MASH DDSM. In this work, we present an optimized MASH-SR hybrid and compare the design with its conventional MASH DDSM and SR counterparts.

Influence of Initial Condition on Wandering Spur Pattern in a MASH-Based Fractional-N Frequency Synthesizer

A Multi-stAge noiSe sHaping Digital Delta-Sigma Modulator (MASH DDSM) is commonly employed as the divider controller in a fractional-N frequency synthesizer. Previous work has considered a time-varying pattern of spurious tones, called wandering spurs, which originate in the DDSM. Two cases have been considered, namely when the fractional part of the division ratio is (i) close to zero or (ii) close to a simple fraction. In both cases, the wandering spur pattern is independent of the initial state of the modulator. This brief considers a third case where the pattern of wandering spurs depends explicitly on the initial state. The phenomenon is explained analytically and simulation results are presented. Theoretical predictions are confirmed with spectral measurements from a representative commercial monolithic fractional-N frequency synthesizer.

Analysis of Wandering Spur Patterns in a Fractional-$N$ Frequency Synthesizer With a MASH-Based Divider Controller

The Multi-stAge noise SHaping Digital Delta-Sigma Modulator (MASH DDSM), which is commonly used as a divider controller in a fractional- $N$ frequency synthesizer, can produce a time-varying periodic pattern of tones in the output spectrum of the synthesizer; these are known as wandering spurs. In this work, a detailed analysis of the cause of wandering spur patterns in a MASH 1-1-1 DDSM-based fractional- $N$ frequency synthesizer, supported by experimental measurements, is presented.

A Design Method for Nested MASH-SQ Hybrid Divider Controllers for Fractional-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$N$ &lt;/tex-math&gt; &lt;/inline-formula&gt; Frequency Synthesizers

Fractional- $N$ frequency synthesizers contain a divider controller which implements the fractional division. The interaction between the quantization noise from the divider controller and nonlinearities within the synthesizer will cause undesirable degradation of the output phase noise performance. The most common divider controller architecture is the Multi-stAge noiSe sHaping Digital Delta-Sigma Modulator (MASH DDSM). Because the MASH DDSM suffers from performance degradation in the presence of nonlinearities, Galton et al. introduced a new divider controller architecture called the Successive reQuantizer (SQ). The SQ is designed to eliminate spurious tones caused by polynomial nonlinearities of a given order. A drawback of the SQ is that its hardware consumption is significantly higher than that of a MASH DDSM. A nested MASH-SQ hybrid has been introduced to achieve similar spectral performance to the SQ but with reduced hardware cost. In this paper, we present a design method for a nested MASH-SQ hybrid divider controller for fractional- $N$ frequency synthesizers.

Mathematical calculation of sequence length in LFSR-dithered MASH digital delta-sigma modulator with odd initial condition

Multi-stAge noise SHaping (MASH) digital delta-sigma modulator (DDSM) with linear feedback shift register (LFSR) dither and odd initial condition is analyzed mathematically to investigate its periodic behavior. We derive the nonlinear equation of the quantization error in each stage to determine the corresponding sequence length. And five useful lemmas are introduced to help cope with the complicated calculation caused by the pseudo-random dither signal.

A Novel Architecture of Pseudorandom Dithered MASH Digital Delta-Sigma Modulator with Lower Spur

A Digital Delta Sigma Modulator (DDSM) is a Finite State Machine (FSM); it is implemented using finite precision arithmetic units and the number of available states is finite. The DDSM always produces a periodic output signal when the input is constant. This paper proposes a novel method of applying periodic dither to a DDSM in order to obtain minimized spurious tones. The effects of adding the pseudorandom dither signal in different stages within the proposed Multi-Stage noise Shaping (MASH) modulator are expressed in the equations, and the results are compared. We present results regarding the periodicity of the quantization noise produced by a MASH modulator with a constant input and a pseudorandom dither signal. The performance is confirmed mathematically, and by simulation.

Maximum Sequence Length MASH Digital Delta–Sigma Modulators

This paper presents a modified structure for the first-order digital delta-sigma modulator (DDSM) which yields the maximum sequence length (N) for all constant digital inputs and for all initial conditions. Using this structure, MultistAge noise-SHaping (MASH) DDSMs are developed which, for a constant input, always have a sequence length of Nl regardless of the initial conditions and input value, where N is the sequence length of each stage and l is the number of the first-order stages used in the MASH. The performance is confirmed mathematically, by simulation, and experimentally.