Multistage Low-noise Amplifiers Research Articles

An integrated LNA‐phase shifter in 65 nm CMOS for Ka‐band phased‐array receivers

SummaryIn this paper, a vector‐sum phase shifter (VSPS) integrated with a wideband high‐gain low‐noise amplifier (LNA) for Ka‐band phased‐array receivers is presented. The digitally controlled VSPS based on the RF phase shifting architecture consists of a modified I/Q signal generator with additional inductor resonance and a programmable variable gain amplifier (VGA) based on Four 3 × 4 transistor arrays. Besides the reduced parasitic effect of the I/Q signal generator, an Equidistant Contraction Technology (ECT) is used in the VGA, to maintain higher phase shift accuracy of the VSPS. A multistage LNA with series inductor peaking is adopted to fulfill the flat wideband gain, where LC resonance networks are used as interstage matching to compensate for gain roll‐off at a higher frequency. Based on simulations in 65 nm CMOS technology, the presented LNA‐Phase shifter has achieved an average NF of 3.24–3.66 dB, and an average gain of 13.1–23.6 dB. Moreover, an RMS phase error of 1.1–12.6°, an RMS gain error of 4.2–5.6 dB, and an RMS magnitude error of 2.1–2.8 dB are maintained across 27–40 GHz, with a 360° phase shift coverage in steps of approximately 2.8125°. The chip consumes 16.83 mW from a 1.2 V supply voltage, and the occupied area is 0.65 mm2.

Novel low noise amplifier approach for deep brain stimulation

This paper presents an analysis for a multi-stage Low Noise Amplifier (LNA) for application on deep brain stimulation. A low noise amplifier (LNA) with high gain, moderate bandwidth and reduced noise is designed and simulated using LT Spice and PTM BSIM4 CMOS models. The novel LNA circuit topology is proposed which uses a cascaded style to improve mid-band gain of an LNA. The proposed LNA achieves a gain margin which ranges between 60-67 (dB), 2X times; Phase Margin which ranges between 145 to 154 (deg), 3X times; Gain which ranges between 66 to 75 (dB), 2X times and bandwidth from kHz to MHz range. The current biasing circuit is used for enhancing stability and gain range. Also, optimal noise figure is achieved with the help of cascading input matching along with source degeneration technique.

A Broadband LNA With Multiple Bandwidth Enhancement Techniques

This letter presents a broadband multistage low-noise amplifier (LNA) in a 0.15- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> m GaAs pseudomorphic high-electron-mobility (pHEMT) process. The LNA employs multiple bandwidth extension techniques, including cascode, feedback, and gain-enhanced source–drain coupled line (SDCL). The SDCL enhances the gain by combining the source and drain signals and compensates the gain roll-off of the amplifier, which is first proposed in this letter to our knowledge. These techniques are adopted in a three-stage monolithic microwave integrated circuit (MMIC) LNA, achieving a wide bandwidth with high gain. The measured results show that the LNA obtains an average gain of 24.7 dB and a noise figure (NF) of 1.7–2.8 dB in 0.5–24 GHz, with a compact chip area of only 1.47 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> .

Novel Design Charts for Optimum Source Degeneration Tradeoff in Conjugately Matched Multistage Low-Noise Amplifiers

Source degenerative feedback is extensively applied in the low-noise amplifier design. The beneficial effects of this technique are well established in the open literature. However, the designer is often left to trial-and-error or optimization procedures to identify the adequate amount of feedback when other linear requirements, such as signal matching, come into play. This issue is even more relevant in multistage designs. In this article, we present a synthesis procedure and the relevant design chart to identify the optimum feedback inductor value on all transistors of an $N$ -stage amplifier to obtain a perfect match at its external ports in conjunction with amplifier noise figure minimization and a specified gain requirement. It is shown that the method is applicable to arbitrary $N$ values although it becomes more elaborate for $N$ greater than 6. The method is deterministic as opposed to optimization or trial-and-error-based procedures. The design flow is illustrated at first through a four-stage design with ideal matching elements and subsequently validated by an monolithic microwave integrated circuit (MMIC) test vehicle designed and realized in the WIN foundry’s Gallium Arsenide PIH1-10 process. The measured performance of the test vehicle is NF = 1.9 dB, 26 dB gain, typical I/O return loss of 15 dB in the 26.5–29.5-GHz bandwidth, and practically ideal behavior at the design frequency of 28 GHz.

A W‐band preamplified MMIC power detector for passive imaging applications

AbstractThis article presents a W‐band preamplified power detector (PD) monolithic microwave integrated circuit (MMIC). The chip consists of a pseudomorphic high electron mobility transistor (pHEMT) PD with a six‐stage low noise amplifier (LNA) in a commercial 0.1‐μm GaAs pHEMT technology. In order to reduce the high risk of oscillating in a multistage LNA, a circulator‐based method for LNA interstage stability simulation, along with the concept of loop gain, is introduced and analyzed. The simulated loop gain of each node of the LNA is calculated through the proposed method to ensure the unconditional stability for the six‐stage LNA. By incorporating the high gain LNA over 32 dB in the front‐end of the PD, the measured chip achieves a peak responsivity of 3.4 MV/W and a minimum noise equivalent power (NEP) of 95 fW/Hz1/2 both at 85 GHz. To the best of the authors' knowledge, the proposed PD exhibits the best responsivity and NEP in published W‐band GaAs PD MMICs.

Integrated Low Noise Amplifier with Capacitive Shunt Feedback Impedance Matching for Radio Astronomy

The noise performance of integrated low noise amplifiers (LNAs) is impaired by on-chip inductors owing to their low-quality factor, especially when inductors are used in the signal path at the input, such as for the inductively degenerated common-emitter amplifier. The inductively degenerated common-emitter configuration is largely used in LNA design, owing mainly to its ability to achieve impedance and noise matching simultaneously. This paper proposes an LNA configuration that achieves impedance matching and noise matching simultaneously without an inductor in the input signal path, owing to capacitive feedback and transistor sizing. Only the resistive component of the optimum noise resistance is matched to the source resistance. The impact of the mismatch due to the reactive component to the noise figure is reduced by the ratio G s /R n . A technique initially developed for the broadband matching of a single-layer microstrip patch antenna is used for the output matching network. Using a 130 nm silicon–germanium heterojunction bipolar transistor process, simulation results indicate a noise figure of 2.3 dB, a gain of 26 dB and S 11 and S 22 that are better than −12 dB at 1.42 GHz. This frequency corresponds to the 21 cm hydrogen line. This novel multi-stage LNA can be used for the detection of electromagnetic radiation from neutral hydrogen atoms from space in radio astronomy and the proposed design methodology can be generalized to LNAs.

Optimization of LNA’s first stage to reduce overall noise figure in multi-stage LNAs

An analytical approach for designing the first stage in multi-stage low noise amplifiers (LNAs) is presented. This paper discusses the first stage optimization for minimizing the overall Noise Figure (NF) with consideration of following stage’s noise. This approach focuses on source impedance optimization of first stage while considering its NF, gain and the effect of the following stage’s NF simultaneously. The proposed approach calculates the first stage’s design parameters to have minimum overall NF in a multi stage LNA while the conventional approach suggests optimum source impedance to achieve minimum NF in first stage. In this paper, it is proved that constant overall-NF contours in Smith chart are different from traditional NF circles and Γopt for best noise performance changes in multi stage LNAs with different NF in adjacent stages. These contours and the optimum source impedance are depicted for specific LNA and compared with its constant NF circles and Γopt. For checking the feasibility of proposed approach and also validation of theoretical and simulation results a discrete LNA in 4–5 GHz using ATF13136 transistor is made. Results show that considering the subsequent circuit’s noise in LNA’s first stage design reduces overall-NF while improves its gain and input matching.

Study of microwave damage effect on HEMT low noise amplifier under different drain voltage bias

The microwave damage effect on high electron mobility transistor (HEMT) low noise amplifier (LNA) under different drain voltage bias is studied using TCAD simulation and experiments. Simulation and experimental results suggest that the damage power thresholds and damage locations of single stage LNA under different drain voltage bias are almost the same. Nevertheless, the output power under zero drain bias is about 5.6dB higher than it under normal (3V) drain bias with the injection of large power microwave pulses. In Addition, the output power relative to it under normal drain bias decreases linearly with the increase of drain bias, following the function of PdB=−1.85Vds+5.7. For multi-stage LNA, the observation using optical microscope reveals that the first and second stage HEMT of LNA under zero drain bias are both damaged while only first stage HEMT of LNA under normal bias is damaged with the injection of same large power microwave pulses, which is consistent with simulated output characteristics results.

A &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\mu $ &lt;/tex-math&gt; &lt;/inline-formula&gt;NMR CMOS Transceiver Using a Butterfly-Coil Input for Integration With a Digital Microfluidic Device Inside a Portable Magnet

This paper describes a 20 MHz micro-nuclear magnetic resonance ( $\mu $ NMR) transceiver (TRX) featuring a butterfly-coil input for chemical/biological assays. It enables integration with a 2D multi-electrode digital microfluidic (DMF) device inside a space-limited portable magnet (0.46 T, 1.25 kg), making multi-sample management compatible with $\mu $ NMR measurements, and supporting electronic automation. The transmitter (TX) incorporates a pulse-sequence synthesizer followed by an inverter-based power amplifier (PA), to emit the exciting pulses for magnetizing the protons of the samples. For the receiver (RX), it is headed by a multi-stage low-noise amplifier (LNA) using NMOS-PMOS-complementary differential pairs, achieving a sub-nV/ $\surd $ Hz input-referred noise at low power. Sixth-order Butterworth low-pass filters constitute the core of the RX I/Q baseband. Their source-follower-based topology allows fast and coherent scaling of all poles by the bias current, reducing the dead-time of the RX for better sensitivity. Fabricated in $0.18~\mu \text {m}$ CMOS, the TRX occupies a die area of 2.1 mm2, consumes 6.6/23.7 mW of power in the TX/RX mode, and demonstrates the feasibility of electronic-automated biological (avidin) and chemical (CuSO4) assays achieving a detection limit on avidin of 0.2 pmol.

A Broadband Multistage LNA With Bandwidth and Linearity Enhancement

Design techniques to enhance bandwidth and linearity of broadband multistage low-noise amplifiers (LNAs) are presented. A feedback amplifier circuit is proposed to compensate for transistor gain roll-off with frequency in other amplifier stages and extend overall bandwidth. Moreover, a transistor width tapering in a multistage LNA is applied to improve linearity. These techniques are adopted in a three-stage monolithic microwave integrated circuit (MMIC) LNA implemented in a 0.1- $\mu \text {m}$ GaAs pHEMT process. The LNA features 18–43 GHz bandwidth, 21.6 dB average gain, and 1.8–2.7 noise figure (NF). It exhibits output 1-dB compression point of 11.5 dBm at 30 GHz and consumes 70 mA bias current from a 2-V supply.

Design of Cascaded Common Source Low Noise Amplifier for S-Band using Transconductance Feedback

Background/Objectives: Now-a-days advancements in CMOS technology increase the demand on transceiver design in the aspect of gain, linearity, power, re-configurability and cost-effectiveness. The performance of RF frontend of transceiver system using MOS device are excellent and found to be the par of 3-5 semiconductor technology. Methods/Statistical Analysis: The first component present in transceiver design is Low Noise Amplifier (LNA) which requires high gain, low noise, better input-output matching, low power, good linearity and stability. Trade off between these performances is more complex when transistors operate at reduced supply voltage and reduced power consumption. So many researchers focus to modify the existing topology by adding active/passive feedback elements and/or using current re-use inductors 2,3. But the latter, suffer from large power consumption. Moreover LNA using cascode configuration offers good gain with low power but the circuit has the limitation of output voltage swing 4. So the proposed work focuses on the design of LNA using transconductance feedback in Common Source (CS) configuration circuits. Findings: At RF frequencies, distributed parasitic of the device dominates thus altering the input-output matching characteristics which degrades gain, noise figure and stability of Low Noise Amplifier. So design of multistage LNA with feedback techniques is necessary to increase the gain. The transconductance feedback used in the design of LNA suits well for increase of gain provided if it is properly designed to ensure stability. The proposed work involves the design of MOS based low noise amplifier using single stage and cascaded Common Source (CS) configuration in S-band. By using the transconductance feedback in CS amplifier, the voltage gain is boosted. Using the extracted small signal equivalents, single stage and cascaded CS amplifier with the transconductance feedback are designed and analyzed. Importance of device parasitic like gate to source capacitance, gate to drain capacitance and the output resistance influence the loop gain. This is brought in the design and emphasizes on the proper utilization of these parasitic in LNA design with transconductance feedback. Using a standard 90 nm CMOS process, LNAs have been demonstrated for 2-GHz frequency (S-band) applications. Operated at a supply voltage of 0.6 V, the gain and noise figure of single stage CS LNA with transconductance feedback are observed to be 17.9 dB and 2.1 dB respectively. It is noted that nearly 17% gain improvement has been achieved with excellent input reflection coefficient of -54.8 dB and low power consumption of 2.92 mW. Similarly, for a cascaded CS amplifier when operated at 0.6V, it is observed that the gain and noise figure are found to be 13.6 dB and 2.38 dB respectively. It is noted that nearly 6.25% increase in gain is achieved with appealing reverse gain of -52. 8 dB when compared to cascaded CS circuit without transconductance feedback. Higher reverse gain ensures the stability of the designed amplifier. Applications: The proposed work is needed in the design of transceivers working at S-band (2 GHz - 8 GHz). Few noticeable applications are: Communication satellites (NASA), weather radar systems, microwave ovens and optical communication which require low power modules. Improvements: This work can be further extended to reconfigure the input matching network so that UWB bandwidth is covered.

An Integrated High-Precision Probe System in 0.18-$\mu{\rm m}$ CMOS for Near-Field Magnetic Measurements on Cryptographic LSIs

This paper presents a fully integrated magnetic probe with a multistage low-noise amplifier (LNA) in a 0.18-μm CMOS process to measure and analyze near-field magnetic map on cryptography LSI chips. is used to pick up near-field magnetic. A three-stage controllable-gain differential LNA integrated with an on-chip inductor used to pick up magnetic near-field amplifies induced voltages of the coil. Moreover, a focused-ion-beam technique is applied to sputter away the Si-substrate area underneath the coil to enhance the coil's performance. A high and controllable-gain amplifier stage with self-bias cascade structure is also proposed for the last-stage LNA. Total gain of the LNA is achieved up to 63 dB at 17.37 MHz in HSPICE post-layout simulation. A high-precision mechanical scanning and monitoring system for the probe are implemented in this paper. Two probes are fabricated with two on-chip pick-up coils with different sizes of 100-μm × 100-μm and 500-μm × 100-μm. Comparisons of two coils are also performed, both in simulation and in measurements. First, evaluations of these probes are performed by measuring the emission of a 100-μm-width microstrip-line through probes' output and the high-precision scanning system. Then, a probe with 100-μm × 100-μm coil and the scanning system are applied to measure and build 7-mm × 9-mm 2-D-distributed magnetic-field maps of a field-programmable gate array (FPGA) operating with a 24-MHz clock on an advanced-encryption-standard encryption core. Magnetic noise maps of the FPGAs surface with several frequency bands are achieved to identify sensitive areas of the clock's information.

Noise measure-based design methodology for simultaneously matched multi-stage low-noise amplifiers

A novel narrow-band design methodology for multi-stage low-noise amplifiers (LNAs) is presented which is based on noise measure and on appropriately designed reactive inter-stage networks. Design formulae are given, in particular, concerning the realisation of the latter networks in T and II configurations, so as to make possible a partially automated design algorithm. As a test vehicle of the presented procedure, the design and realisation of a three-stage K-band LNA is discussed and the corresponding measured results are shown.

Low-power multistage low noise amplifiers for wireless sensor networks

Two multistage low noise amplifiers are presented. Supply voltages are 0.4 V and 1.2 V, respectively, with bias currents of 4.4 mA and 2.09 mA. Both designs are suitable for low-power applications in the 2.4 GHz band. Circuits have been implemented and simulated using a UMC 130 nm RF-CMOS process. The amplifiers provide, respectively, a 14.4 dB power gain, a noise figure NF <2.2 dB and a 1-dB compression point of −19.9 dBm, whereas dissipating 1.77 mW and a 12.7 dB power gain, a noise figure NF <1.59, a 1-dB compression point of −15.45 dBm with a 2.5 mW power dissipation. Such performance makes these designs suitable for wireless sensor network applications such as ZigBee.

Ka-band multistage MMIC low-noise amplifier using source inductors with different values for each stage

A Ka-band three-stage monolithic microwave integrated circuit (MMIC) low-noise amplifier using source inductors with different values for each stage has been developed for use in active phased-array receiver modules. The three-stage MMIC low-noise amplifier with 0.15/spl times/120 /spl mu/m/sup 2/ AlGaAs-InGaAs pHEMTs has achieved a noise figure of 1.6 dB, a gain of 22.8 dB, an input return loss of 29 dB, and an output return loss of 24 dB at 28 GHz by optimizing the values of source inductors for each stage. The minimum noise figure was 1.3 dB at 30 GHz.

Relating μ-wave mapped data to physical parameters for MODFETs

Modulation doped Al 0.2Ga 0.8As/In 0.3Aa 0.3As high electron mobility transistors (HEMT) were statistically characterized at μ-wave frequencies. The results provided information to optimize transistor fabrication technology and as well to investigate transistor reliability and reproducibility to allow the design of multi stage low noise amplifiers (LNAs) [1].

Technical memorandum: versatile strategy for CAD of multistage low-noise amplifiers

The introduction of a novel performance chart which allows the selection of simultaneous noise, gain and VSWR specifications for a multistage low-noise amplifier equipped with given active devices is described. In addition, the individual goal function to be assigned to each equiliser network to fulfil the chosen specifications is provided. A design example is also included.

Optimum Noise Measure Terminations for Microwave Transistor Amplifiers (Short Paper)

The noise performance of the individual stages in a multistage low-noise amplifier can be quantified by means of the noise measure as proposed by Haus and Adler [4]. The minimization of the noise measure of a given active two-port device is of direct interest to the designer of such amplifiers. A new means of obtaining circles of constant noise measure in the source reflection coefficient plane is presented here. These circles can be used to determine the value of the minimum noise measure for a given active device and the associated source termination. The validity of the new method has been verified by comparison with results obtained using existing equations for the admittance plane and also by experiment.