Abstract
Design techniques to enhance bandwidth and linearity of broadband multistage low-noise amplifiers (LNAs) are presented. A feedback amplifier circuit is proposed to compensate for transistor gain roll-off with frequency in other amplifier stages and extend overall bandwidth. Moreover, a transistor width tapering in a multistage LNA is applied to improve linearity. These techniques are adopted in a three-stage monolithic microwave integrated circuit (MMIC) LNA implemented in a 0.1- $\mu \text {m}$ GaAs pHEMT process. The LNA features 18–43 GHz bandwidth, 21.6 dB average gain, and 1.8–2.7 noise figure (NF). It exhibits output 1-dB compression point of 11.5 dBm at 30 GHz and consumes 70 mA bias current from a 2-V supply.
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