Multistage Interconnection Networks Research Articles

VA-DE: Valuable ATAPE with dynamic embedding and super-pipeline scheduling on partitionable multistage interconnection [formula omitted

The optimal ATAPE (all-to-all personalized exchange) is a key solution to achieve the optimal communication in parallel matrix-transposition, parallel fast-Fourier-transformation, etc. The ATAPE has been extensively studied on static networks and dynamic binary-switch MINs (multistage interconnection networks). Recently, the ultimate ATAPE was successfully embedded on MINs+ and the fast crossbar of MINs+. However, the MINs+ cannot be partitioned for multiple tasks and the crossbar of MINs+ is more expensive and less subsystem-utilization. Therefore, this paper proposes the prototype of the x×x crossbar of partitionable MINs+ (PMINs+) using I/O cross-control switches and the generalized d-nary-switch MINs+. In addition, the optimal VA-DE (valuable ATAPE with dynamic embedding) with triple-right scheduling (right-task, right-section, right-time) is presented for multiple tasks of flexible sizes N″=N/2t (where t≤log2x) and the efficient subsystem-utilization on the PMINs+. New partitionable ATAPE embedding and automatic mapping for the partitionable section y(=0 to x−1) are Dy=Sy⊕Cly (global) and lDy=(Dy%N″)⊕cz (local) using double-jumping controls Cly=(yN/x+l)modN (to right section) and cz=zN″/x (to right subtask), incorporated with super-pipelining for outperforming optimal time O(N/x) over O(N), the best of existing ATAPEs. In experiments, remarkable speedup and throughput were strongly confirmed on the simulated PMIN+ systems.

4DGIN-3: A new design layout of 4-disjoint gamma interconnection network

Various multistage interconnection networks have been proposed in the literature and utilized in commercial projects. But there exists a further scope of improvement and the need for new fault tolerant multistage interconnection networks, which can withstand multiple switch or link failures. Recently, design layouts of four disjoint paths gamma interconnection networks have been proposed and named as 4DGIN-1 and 4DGIN-2, respectively. These proposed design layouts of 4DGINs produce different number of alternative paths ranging from five to seven for different tag values. In this paper, a new variant, viz., 4DGIN-3 is introduced, which generates four disjoint paths similar to 4DGIN-1 and 4DGIN-2 but with a total of six number of alternative paths for every tag value. This feature of the proposed design, in turn, results in same reliability for each tag value at various assumed reliability of switching elements despite having the similar topology and hardware cost as that of the earlier 4DGINs. A comparison of the proposed design with the existing 4DGINs has also been provided in this paper.

A New SEN Minus: Design and Reliability Measures

Multistage interconnection networks (MIN) are becoming attractive choice as they provide fast and efficient communication at reasonable cost, for multiprocessing systems. Shuffle exchange network (SEN) are specific class of MIN characterized as lowest cost unipath MIN. Several developments have made SEN MIN fault tolerant with redundant paths by increasing the number or size of switching elements (SE). However, recently [Formula: see text] has been advanced by reducing the number of stages, but has serious limitation namely: (i) partial connectivity of each source–destination pair, (ii) unique path. A new method has been proposed in this paper to develop a new topology of MIN with one stage less than the basic unipath MIN of same class with multiple and disjoint path facility that mitigates the shortcomings of the above network and is truly [Formula: see text] MIN. Due to less number of stages used in the proposed network communication delays are also reduced as the path length is reduced. Parametric performances such as Terminal, Broadcast and Network Reliabilities, MTTF, Bandwidth have been computed for different network sizes and demonstrated that it not only outperforms other SEN variants, but has improved features of fault tolerance all because of disjoint minimal path set. Further the comments generated previously in literature about better reliability performance of [Formula: see text] than other two networks [Formula: see text] have been refuted and have demonstrated that [Formula: see text]2 network has better performance than other two for larger network size. Also it can be concluded that the performance of proposed [Formula: see text] is best among all these networks.

Multistage interconnection networks reliability analysis

Multistage interconnection network (MIN) is an interconnection system consisting of multiple layers of interlinked switching elements arranged in a predefined topology allowing processor and memory modules to communicate with each other. Reliability evaluation for MINs is quite evident, as these measures provide user-oriented performance assessment. Reliability analysis of two important interconnection network layouts (shuffle and gamma) are computed and compared here. Reliability expressions are computed mathematically by the path set-based analytical methods using the MVI algorithm.

Multi-source multi-terminal reliability evaluation of interconnection networks

Multistage interconnection networks (MINs) are often used as switching fabrics in parallel and distributed systems designed to provide fast and efficient communication between high-capacity processors. To ensure desired performance of the networks, the reliability evaluation of MIN is quite evident. Reliability studies on MINs evaluated only traditional parameters (two/broadcast/all terminal reliability). With increasing number of input and output nodes in supercomputer environment reliability evaluation of multi-cast nodes is mandatory. A simple and efficient algorithm, Path Tracing Algorithm proposed to trace minimal path sets of any MINs and then associated reliability (or unreliability) expressions are evaluated. The algorithm found quite simple and robust to trace the minimal path sets of a variety of networks and evaluates Multi-source multi-terminal node reliability of any multistage interconnection networks. Total redundant and disjoint paths for each source---destination pair are also evaluated by using the algorithm. Reliability of various MINs are evaluated, analyzed and compared here.

Reliability Analysis of Multistage Interconnection Networks

Multistage interconnection networks (MINs) are widely used for reliable data communication in tightly coupled large‐scale multiprocessor systems. Reliability evaluation of interconnection networks is still a challenge owing to high complexity. Need of reliability evaluation for MINs is quite evident as these measures provide user‐oriented performance. Terminal pair reliability (TPR) is the most commonly used reliability performance index of MINs. This paper provides a global view of different reliability measures and approaches for evaluation of these measures. Based on the critical literature review, shortcomings are identified and analyzed. Then the multi‐variable inversion algorithm is applied to evaluate the reliability of one of the most common MINs, namely, Omega network, in a compact form. Terminal, broadcast, and network reliability for the Omega, Omega with an additional stage (Omega+), and Omega with two additional stages (Omega+2) systems are analyzed and compared. Then we extend our work to trace the minimal path sets of various MINs, and terminal pair reliabilities are evaluated and compared. Copyright © 2015 John Wiley & Sons, Ltd.

Fault Tolerant Interconnection Network Design

ABSTRACTAdvances in parallel and distributed computing have made interconnection networks a potential networking alternative to meet the growing demands of high-performance computing. Multiple processors need to communicate with each other and with memory modules. Multi-stage interconnection networks (MINs) provide a communication medium in multi-processor system as they interconnect a number of processors and memory modules. Design of MIN has to meet ever better performance by providing more disjoint paths, low hardware cost, higher reliability, and rerouting capabilities tolerating any switch/link failures. New architecture of fault tolerant multistage interconnection network layout is proposed. Proposed layout is a multipath MIN providing four disjoint paths for all the source and destination pairs. It has full access and dynamic rerouting property under any switch/link failures. Collision problems are effectively handled by this dynamic rerouting capability by automatically changing their routing path during any switch/link faults. Proposed network design is highly reliable with higher fault-tolerant capability than other interconnection networks topologies. Evaluated terminal pair reliability for new layout is found to be higher than other MINs.

Embedding the optimal all-to-all personalized exchange on multistage interconnection networks[formula omitted

All-to-all personalized exchange (ATAPE) is an inspired process to speedup the parallel and distributed computing. Recently, ATAPE algorithms were successfully applied on multistage interconnection networks (MINs), including baseline and butterfly networks. However, routing of those algorithms on MINs relies on switch-patterns for stage-control from sources (S), which is a half-routing solution since they cannot perform a full self-routing with the (S, D) protocol for all MINs. In this paper, first we propose a full-routing solution of the realizing ATAPE on a class of d-nary-switch MINs+ (i.e., baseline+, butterfly+, etc.). Our ATAPE can be embedded on-chip effectively for not only (S, D) self-routing but also stage-/switch-control routing. Two embedded ATAPE functions incorporate with multi-stage pipelining are proposed in optimal O(N+log2N): 1. a (default) static function D=S XOR (C+order) mod N and 2. an (optional) f-in-1 dynamic function D=ρ [(S+C+order) mod N] with the incrementing counter C=0 to N−1. Second, we introduce a crossbar of MINs+ with fewer delay-stages to achieve the ultimate ATAPE embedding. Finally, experimental results of applying ATAPE on such MINs+ are confirmed fruitfully, including the ATAPE-based NxN-matrix transposition in O(N+log2N), which yields the significant speedup.

Reliability analysis of multilayer multistage interconnection networks

Multistage interconnection networks (MINs) play a key role in the performance of parallel computers and multiprocessor systems. A non-negligible demand on today's modern systems is to deliver multicast traffic. Therefore, design of efficient MINs that meets the routing requirement is vital. One of the main ideas to cope with this problem is the use of replicated MINs. However, one of the major concerns about these networks is the problem of unnecessary layer replication in the first stages, which recently proposes a new idea called multilayer MINs. Previous analyzes demonstrated that this new idea could lead to cost-effective topologies that had a very close performance to the replicated MINs in terms of throughput. Also, these analyzes indicate that these networks outperform replicated MINs in terms of delay. However, another critical parameter to prove the performance of most systems is reliability. Therefore, in this paper, we will focus on two essential parameters of cost and reliability to achieve both objectives; first, evaluating the performance of multilayer MINs in terms of reliability, second, to find the best topology among the multilayer MINs introduced in previous works in terms of cost-effectiveness (mean time to failure/cost ratio).

Formulating broadcast reliability equations on multilayer multistage interconnection networks

A non-negligible demand on today's modern interconnection networks is to deliver multicast traffic. One of the new ideas to cope with this problem is to use the multilayer multistage interconnection networks (MLMINs). On the other hand, another critical parameter to prove the performance of most systems is reliability. Therefore, in this paper, our focus is to formulate the reliability equations on MLMINs to achieve two objectives: First, development of analytical methods using reliability equations to present an exact solution for computing the reliability of MLMINs, second, preparing a basis for calculating the optimal values for topological parameters of MLMINs ($$G_\mathrm{S}, G_\mathrm{F}$$GS,GF, and $$G_\mathrm{L}$$GL) in terms of reliability.

Flattening: An efficient approach to improving the performance of conventional MINs

Numerous conventional interconnection networks have been designed in a way in which they use indirect or multistage topologies. The reason behind this idea is the fact that such topologies can minimize the network hop count. However, the constraints of technology and packaging have given impetus for fundamental changes in the approach to designing topologies. Increasing the radix of the network׳s routers lowers the total cost of the network, which is related to the number of routers׳ pins and connectors. This increase also results in lowering the power consumption, which plays a crucial role in the performance. Kim, Dally and Abts have provided a cost-efficient topology for high-radix networks, named the flattened Butterfly. They have shown that this approach is comparable to the conventional Butterfly networks with regard to cost. It is much the same as a Folded-Clos topology in terms of the performance per cost ratio under adversarial traffic, whilst under benign traffic, the flattened Butterfly has approximately twice this ratio. In this paper, we have generalized the idea of flattening to all Delta networks, in addition to some non-Delta ones such as Beneš and Clos. Moreover, the conditions on which multistage networks can be converted to the flattened ones have been generally provided. All the mentioned networks have also been compared with another cost-efficient topology, named the HyperX, in order to gain deep insight into the key facets of the microarchitecture of high-radix networks. On the other hand, advances in designing digital circuits and reduction in their size rely upon knowledge in nano-electronics for refinements of the standard copper interconnect technology. This copper interconnects have become a major performance bottleneck in Multistage Interconnection Network (MIN) platforms. Consequently, a minor contribution of this paper is the performance assessment of the aforementioned networks using the Carbon NanoTube (CNT) technology under trace-driven and synthetic traffic patterns; inasmuch as this technology has been introduced as one of the six most important architectures in future digital systems. CNT is considered to be a promising technology in the design and fabrication of the next-generation chips since it is capable of handling extremely high current densities for a long time without considerable performance degradation. Although the comparative study of different networks with various parameters is the main goal, it should be taken into consideration that in some situations, these parameters provide similar conditions in different networks. As such, they can be combined with an efficient method to present a simple model. Finally, we have used data mining in order to reach a unified and meaningful performance parameter.

Evaluating failure rate of fault-tolerant multistage interconnection networks using Weibull life distribution

Fault-tolerant multistage interconnection networks (MINs) play a vital role in the performance of multiprocessor systems where reliability evaluation becomes one of the main concerns in analyzing these networks properly. In many cases, the primary objective in system reliability analysis is to compute a failure distribution of the entire system according to that of its components. However, since the problem is known to be NP-hard, in none of the previous efforts, the precise evaluation of the system failure rate has been performed. Therefore, our goal is to investigate this parameter for different fault-tolerant MINs using Weibull life distribution that is one of the most commonly used distributions in reliability. In this paper, four important groups of fault-tolerant MINs will be examined to find the best fault-tolerance techniques in terms of failure rate; (1) Extra-stage MINs, (2) Parallel MINs, (3) Rearrangeable non-blocking MINs, and (4) Replicated MINs. This paper comprehensively analyzes all perspectives of the reliability (terminal, broadcast, and network reliability). Moreover, in this study, all reliability equations are calculated for different network sizes.

Fault Tolerant Routing in Irregular ModifiedShuffle Network

Interconnection networks (IN) play very important role in various parallel processing applications. The connectivity pattern used in interconnection networks greatly determines the performance of the system. Multistage Interconnection Network is also an IN. The interconnection pattern used also determines the fault tolerance of the network. This paper introduces a new irregular fault tolerant multistage interconnection network named Irregular Modified Shuffle Network (IMSN). IMSN is analyzed in terms of fault tolerance and it has been observed that IMSN provides more alternate paths than existing networks such as Improved Four Tree Network (IFTN), Modified Alpha Network (MALN) and New Irregular Augmented Shuffle Network (NIASN).

The performance of MIN-based switch fabrics

A new method for the performance analysis of multistage interconnection networks (MINs) is presented. It supports modelling and analysis of switch fabrics built on such switching networks. The method is based on the idea of a generalized traffic source outlined in the paper. Using the generalized traffic idea, the new method overcomes the problems and limitations encountered in existing MIN performance analysis methods and can capture a larger variety of switching networks. Application of the proposed method and its generalizability are discussed. A higher flexibility of this new method to consider diverse traffic patterns is also reported. Sample results of the analysis proposed in this contribution are compared with the results of earlier methods and found superior. Simulation validation is also provided. The method is simple yet powerful enough to help designers to find the optimal structure of switching network for building a scalable router.

Reliable multistage interconnection network design

High-performance supercomputers generally comprise millions of CPUs in which interconnection networks play an important role to achieve high performance. New design paradigms of dynamic on-chip interconnection network involve a) topology b) synthesis, modeling and evaluation c) quality of service, fault tolerance and reliability d) routing procedures. To construct a dynamic highly fault tolerant interconnection networks requires more disjoint paths from each source-destination node pair at each stage and dynamic rerouting capability to use the various available paths effectively. Fast routing and rerouting strategy is needed to provide reliable performance on switch/link failures. This paper proposes two new architecture designs of fault tolerant interconnection networks named as reliable interconnection networks (RIN-1 and RIN-2). The proposed layouts are multipath multi-stage interconnection networks providing four disjoint paths for all the source-destination node pairs with dynamic rerouting capability. The designs can withstand switch failures in all the stages (including input and output stages) and provide more reliability. Reliability analysis of various MIN architectures is evaluated. On comparing the results with some existing MINs it is evident that the proposed designs provides higher reliability values and fault tolerance.

A New Fault-Tolerant Interconnection Network

An interconnection network plays vital role for faster communication in parallel processing environment. The performance of interconnection network highly depends upon fault tolerance capability .The fault tolerance can be achieved by providing multiplicity of paths between any pair of source and destination nodes and an efficient fault tolerant routing technique. In our designing approach of a new interconnection network, these two primary objectives can be achieved. We modified the structure of fully chained combining switch multistage interconnection network so that the new modified network can tolerate multiple links or switches faults dynamically. The cost of our network is less in comparison to the existing networks.

Improving the reliability of the Benes network for use in large-scale systems

Systems with high computational capabilities are usually made of a large number of processing elements in order to solve complex problems efficiently. To achieve this purpose, the processing elements must be able to communicate with each other, which can be provided by interconnection networks. Meanwhile, multistage interconnection networks (MINs) are often recommended for use in such systems due to the efficiency and cost-effectiveness. However, there is a fundamental problem in the general structure of these networks called blocking. An important class of MINs is rearrangeable non-blocking MINs that can be used as a cost-effective solution to cope with the blocking problem. Benes network is one of the most popular rearrangeable non-blocking MINs, which has been considered by many researchers over the years. And yet its reliability improvement is an important factor that must be considered in the review of most systems, especially large-scale ones. Based on previous works, there are three main approaches to improve the reliability of MINs: (1) Adding a number of stages to MIN. (2) Using multiple MINs in parallel. (3) Using replicated MINs. In this paper, in order to find the best solution to improve the reliability of the Benes network, all three of these methods are investigated. Reliability analyses show that the use of multiple parallel Benes networks can obtain more advantages than other methods for Benes network. The approach improves the Benes network to be used in large-scale systems in various aspects of reliability namely time-independent terminal reliability, time-independent broadcast reliability, time-dependent terminal reliability, and time-dependent broadcast reliability.

GreedyZero Algorithms for Conflict-free Scheduling in Low Stage Interconnection Network

Abstract Low Stage Interconnection Networks are a class of Interconnection Networks. They have been generated from Multistage Interconnection Networks (MINs). Although the conflict in the optical switches, there is the consid- erable interest to use the optical technology in interconnection networks implementation. To avoid this problem, GreedyZero algorithms has been assigned to the Low Stage Interconnection Networks for improving the network performance by reducing the number of passes. The results marked nearly 50% reduction in the number of passes and proved improvement of scheduling in the Low Stage Interconnection Networks by GreedyZero algorithms.

English

The reliability can be measured in terms of MTTF i.e. Mean Time To Failure. It is defined as expected time elapsed before some source is disconnected from some destination. In this paper Optimistic and Pessimistic MTTF Bounds of proposed Multistage Interconnection Network (MIN) New Irregular Augmented Shuffle Exchange Network (NIASN) have been evaluated and compared with existing similar class of MINs Augmented Baseline Network (ABN).

Performance evaluation of generic multi-stage interconnection networks with blocking and back-pressure mechanism

Multi-stage interconnection networks (MINs) have frequently been proposed as connection means in traditional parallel systems and networks-on-chip. Most of the existing papers consider some specifi...