Fault Tolerant Interconnection Network Design

Abstract

ABSTRACTAdvances in parallel and distributed computing have made interconnection networks a potential networking alternative to meet the growing demands of high-performance computing. Multiple processors need to communicate with each other and with memory modules. Multi-stage interconnection networks (MINs) provide a communication medium in multi-processor system as they interconnect a number of processors and memory modules. Design of MIN has to meet ever better performance by providing more disjoint paths, low hardware cost, higher reliability, and rerouting capabilities tolerating any switch/link failures. New architecture of fault tolerant multistage interconnection network layout is proposed. Proposed layout is a multipath MIN providing four disjoint paths for all the source and destination pairs. It has full access and dynamic rerouting property under any switch/link failures. Collision problems are effectively handled by this dynamic rerouting capability by automatically changing their routing path during any switch/link faults. Proposed network design is highly reliable with higher fault-tolerant capability than other interconnection networks topologies. Evaluated terminal pair reliability for new layout is found to be higher than other MINs.