Multiprocessor System-on-chip Research Articles

CPU-GPU Cooperative QoS Optimization of Personalized Digital Healthcare Using Machine Learning and Swarm Intelligence.

In recent decades, the rapid advances in information technology have promoted a widespread deployment of medical cyber-physical systems (MCPS), especially in the area of digital healthcare. In digital healthcare, medical edge devices empowered by CPU-GPU (Graphics Processing Unit) cooperative multiprocessor system-on-chips (MPSoCs) have a great potential in processing and managing the massive amounts of health-related data. However, most of the existing works on CPU-GPU cooperative MPSoCs cannot maintain a high-precision workload estimation since they simply leverage the worst-case execution cycles to pessimistically predict the workload of digital healthcare applications. Besides, they neglect the personalized requirements of individual healthcare applications and the lifetime reliability demands of heterogeneous CPU-GPU cores. As a result, the normal functions of medical edge devices and the quality-of-services (QoS) of digital healthcare applications are likely to suffer from underlying failures and degradation. In this paper, we explore CPU-GPU cooperative QoS optimization of personalized digital healthcare applications running on reliability guaranteed edge devices with the help of machine learning and swarm intelligence techniques. We first develop two novel predictors: one is a machine learning based predictor for application workload estimation, and the other is a feature-driven predictor for application QoS estimation. We then incorporate the two predictors into a swarm intelligent application scheduling scheme upon the cooperative dual-population evolutionary algorithm (c-DPEA) to find optimal application mapping and partitioning settings. Experimental results show that our solution not only augments the average QoS of whole digital healthcare applications by 15.7%, but also balances the QoS of individual digital healthcare applications by 64.3%.

FPGA-enhanced system-on-chip for finger vein-based biometric system using novel DL model

In an era dominated by technology, the imperative for robust personal authentication in electronic information systems becomes increasingly evident. A secure and dependable solution to address this need is biometric authentication. Due to their intrinsic features of being universal, unique, and fraud-resistant, finger vein-based recognition systems have gained importance. Veins provide an efficient barrier against misleading methods since they are buried under the skin and undetectable to human sight. While many researchers focus on advanced technology for finger-vein-based authentication systems, existing research has often overlooked significant challenges, such as short datasets, high computational complexity, and a lack of efficient and lightweight feature descriptors. This paper proposes a unique method for automated Finger Vein Recognition (FVR) based on a fusion model known as “CNN-ViT” for FVR. Transfer learning-based Convolutional Neural Network (CNN) models, such as Inception-V3 and ResNet-50, compute the correlation of adjacent pixels to process texture-based features. Furthermore, shape-based features are processed using the vision transformer (ViT) model to determine the relationship between distant pixels. The combination of these three models enables the learning of textural features based on forms, contributing to more effective finger vein identification. In addition to our databases, we utilize two benchmark databases, FV-USM and SDUMLA-HMT, to validate our experiments. Our proposed approach achieves outstanding accuracy values of 99.95 %, 98.9 %, and 97.78 % on both the benchmark and our datasets. When compared to previous methods, the proposed Deep Learning (DL) model outperforms state-of-the-art models, demonstrating higher recognition rates and accuracy. To prototype the proposed FVR system, a Zynq XCZU4EV UltraScale + Multiprocessor System-On-Chip (MPSoC) was employed. The proposed model exhibits high throughput and competitive power efficiency, making it an excellent choice for scenarios where computing performance is critical, albeit utilizing more power and resources. This was established through a comprehensive examination of FPGA resource utilization and performance metrics.

Energy-aware task scheduling for streaming applications on NoC-based MPSoCs

Streaming applications are being extensively run on portable embedded systems, which are battery-operated and with limited memory. Thus, minimizing the total energy consumption of such a system is important. We investigate the problem of offline scheduling for streaming applications composed of non-preemptible periodic dependent tasks on homogeneous Network-on-Chip (NoC)-based Multiprocessor System-on-Chip (MPSoCs) such that their total energy consumption is minimized under memory constraints. We propose a novel unified approach that integrates task-level software pipelining with Dynamic Voltage and Frequency Scaling (DVFS) to solve the problem. Our approach is supported by a set of novel techniques, which include constructing an initial schedule based on a list scheduling where the priority of each task is its approximate successor-tree-consistent deadline such that the workload across all the processors is balanced, a retiming heuristic to transform intra-period dependencies into inter-period dependencies for enhancing parallelism, assigning an optimal discrete frequency for each task and each message using a Non-Linear Programming (NLP)-based algorithm and an Integer-Linear Programming (ILP)-based algorithm, and an incremental approach to reduce the memory usage of the retimed schedule in case of memory size violations. Using a set of real and synthetic benchmarks, we have implemented and compared our unified approach with two state-of-the-art approaches, RDAG+GeneS (Wang et al., 2011) , and JCCTS (Wang et al., 2013a). Experimental results show that our approach’s maximum, average, and minimum improvements over RDAG+GeneS (Wang et al., 2011) are 31.72%, 14.05%, and 7.00%, respectively. Our approach’s maximum, average, and minimum improvement over JCCTS (Wang et al., 2013a) are 35.58%, 17.04%, and 8.21%, respectively.

An Approach to the Systematic Characterization of Multitask Accelerated CNN Inference in Edge MPSoCs

Deep Learning is ubiquitous today and is increasingly moving from the cloud down to the edge of networked infrastructures, where it enables embedded applications to perform complex inference tasks close to the data sources, reducing long-distance data movement and alleviating the need for a powerful cloud infrastructure. Edge-class multi-processor system on chip (MPSoC) devices featuring an on-chip FPGA fabric offer key advantages for Deep Learning inference tasks, especially for complex applications where multiple models may be run concurrently in the same platform. In this work, we propose an approach and a practical framework for the systematic characterization of multithreaded Deep Learning inference on edge FPGA MPSoCs. We instantiate the framework into a real-world MPSoC platform, targeting Xilinx Vitis-AI as a representative example of a commercial Deep Learning acceleration toolkit for edge environments. We design a comprehensive experimental campaign and apply it to the platform for several convolutional neural networks, each trained on three different datasets. We show that our approach can be used for both hardware- and software-level analysis of a target system. Among other findings, the analysis revealed a suboptimal behavior of the underlying toolkit runtime, involving the utilization of the accelerator cores and the uneven software latency of the support library, influenced by the shapes of the input tensors.

POEM: Performance Optimization and Endurance Management for Non-volatile Caches

Non-volatile memories (NVMs) with their high storage density and ultra-low leakage power offer promising potential for redesigning the memory hierarchy in next-generation Multi-Processor Systems-on-Chip (MPSoCs). However, the adoption of NVMs in cache designs introduces challenges such as NVM write overheads and limited NVM endurance. The shared NVM cache in an MPSoC experiences requests from different processor cores and responses from the off-chip memory when the requested data is not present in the cache. Besides, upon evictions of dirty data from higher-level caches, the shared NVM cache experiences another source of write operations, known as writebacks . These sources of write operations: writebacks and responses, further exacerbate the contention for the shared bandwidth of the NVM cache, and create significant performance bottlenecks. Uncontrolled write operations can also affect the endurance of the NVM cache, posing a threat to cache lifetime and system reliability. Existing strategies often address either performance or cache endurance individually, leaving a gap for a holistic solution. This study introduces the Performance Optimization and Endurance Management (POEM) methodology, a novel approach that aggressively bypasses cache writebacks and responses to alleviate the NVM cache contention. Contrary to the existing bypass policies which do not pay adequate attention to the shared NVM cache contention, and focus too much on cache data reuse, POEM’s aggressive bypass significantly improves the overall system performance, even at the expense of data reuse. POEM also employs effective wear leveling to enhance the NVM cache endurance by careful redistribution of write operations across different cache lines. Across diverse workloads, POEM yields an average speedup of \(34\% \) over a naïve baseline and \(28.8\% \) over a state-of-the-art NVM cache bypass technique, while enhancing the cache endurance by \(15\% \) over the baseline. POEM also explores diverse design choices by exploiting a key policy parameter that assigns varying priorities to the two system-level objectives.

Evaluation and validation of efficient hierarchical interconnection in multi-processor system on chip

ABSTRACT Multiprocessor system-on-chip (MPSoC) is increasingly used in today’s complicated embedded systems. This paper uses an efficient Hierarchical Interconnection Framework (EHIF) to improve throughput and latency over traditional 3D mesh NoC. The suggested router is hierarchical with one module handling inter-layer communication and intra-layer communication. The EHIF compares well to the traditional 3D mesh in terms of area and power consumption. The EHIF method reduced the execution time without increasing the memory buffer size to optimise time and memory. It achieves a high performance ratio, throughput, low power consumption, latency and delay compared to other methods

Automatic Fecal Eggs Counting in Ruminants Using Xilinx DPU

Parasite control is vital in the cattle industry. Infection control is based on counting parasite eggs on samples obtained from animals, and processed later in laboratories by human technicians using optical microscopes. This traditional monitoring method affects the yield of production, delaying the start of treatment of infected animals. It also implies an additional cost of mobility of the veterinary expert who determines the treatment. Therefore, it is convenient to have a portable device for automatic fecal egg counting. This work presents an embedded algorithm for this type of analysis, with the ability to implement a portable solution. The implementation is based on Deep Learning, running on a MPSoC (Multiprocessor System-on-Chip) using Xillinx DPU. Our proposal has resulted in significantly lower sample processing time compared to other existing solutions, greater flexibility and a low power consumption.

TROP: TRust-aware OPportunistic Routing in NoC with Hardware Trojans

Multiple software and hardware intellectual property (IP) components are combined on a single chip to form Multi-Processor Systems-on-Chips (MPSoCs). Due to the rigid time-to-market constraints, some of the IPs are from outsourced third parties. Due to the supply-chain management of IP blocks being handled by unreliable third-party vendors, security has grown as a crucial design concern in the MPSoC. These IPs may get exposed to certain unwanted practises like the insertion of malicious circuits called Hardware Trojan (HT) leading to security threats and attacks, including sensitive data leakage or integrity violations. A Network-on-Chip (NoC) connects various units of an MPSoC. Since it serves as the interface between various units in an MPSoC, it has complete access to all the data flowing through the system. This makes NoC security a paramount design issue. Our research focuses on a threat model where the NoC is infiltrated by multiple HTs that can corrupt packets. Data integrity verified at the destination’s network interface (NI) triggers re-transmissions of packets if the verification results in an error. In this article, we propose an opportunistic trust-aware routing strategy that efficiently avoids HT while ensuring that the packets arrive at their destination unaltered. Experimental results demonstrate the successful movement of packets through opportunistically selected neighbours along a trust-aware path free from the HT effect. We also observe a significant reduction in the rate of packet re-transmissions and latency at the expense of incurring minimum area and power overhead.

Comparative analysis of 2D mesh topologies with additional communication links for on-chip networks

Multiprocessor system-on-chip (MPSoC) is playing a vital role in recent embedded technologies. One of the main challenges of this system is its communication bottleneck which limits performance scaling capabilities. In order to overcome this restriction, on-chip interconnection networks have been proposed. Several topologies have been suggested in the literature, but the most popular one remains the mesh topology due to its systematic and scalable design structure. Although, the functionality and performance of network-based mesh topologies degrade significantly with growing system size, which results in the network diameter and the dependency on small bisection width. A wide range of modified designs has been proposed in the literature with various types of additional links to improve the network performance. However, these links result in additional cost overhead on the system in terms of area, energy, and power consumption. Among the selected competitor meshes, it is observed that the link design of d-Torus produces high performance at elevated communication costs. The design of the CBP-Torus is less complex and results in lower communication costs compared to d-Torus with similar performance. The selection of an appropriate mesh-type topology of the target application is, therefore, a tradeoff between the performance and cost of the network. This paper analyzes the impact of additional links on the performance of on-chip mesh architectures. The comparative analysis includes performance characteristics, structural complexity, power consumption, and area utilization. This research work provides a roadmap for the designers to choose the most appropriate topology for a particular design.

Routing Techniques in Network-On-Chip Based Multiprocessor-System-on-Chip for IOT: A Systematic Review

Routing techniques (RTs) play a critical role in modern computing systems that use network-on-chip (NoC) communication infrastructure within multiprocessor system-on-chip (MPSoC) platforms. RTs contribute greatly to the successful performance of NoC-based MPSoCs due to traffic congestion avoidance, quality-of-service assurance, fault handling and optimisation of power usage. This paper outlines our efforts to catalogue RTs, limitations, recommendations and key challenges associated with these RTs used in NoC-based MPSoC systems for the IoT domain. We utilized the PRISMA method to collect data from credible resources, including IEEE Xplore ®, ScienceDirect, Association for Computing Machinery and Web of Science. Out of the 906 research papers reviewed, only 51 were considered relevant to the investigation on NoC RTs. The study addresses issues related to NoC routing and suggests new approaches for in-package data negotiating. In addition, it gives an overview of the recent research on routing strategies and numerous algorithms that can be used for NoC-based MPSoCs. The literature analysis addresses current obstacles and delineates potential future avenues, recommendations, and challenges analyzing techniques to assess performance utilizing metrics within the TCCM framework.

High-Throughput MPSoC Implementation of Sparse Bayesian Learning Algorithm

In the field of sparse signal reconstruction, sparse Bayesian learning (SBL) has excellent performance, which is accompanied by extremely high computational complexity. This paper presents an efficient SBL hardware and software (HW&SW) co-implementation method using the ZYNQ series MPSoC (multiprocessor system-on-chip). Firstly, considering the inherent challenges in parallelizing iterative algorithms like SBL, we propose an architecture based on the iterative calculations implemented on the PL side (FPGA) and the iteration control and input management handled by the PS side (ARM). By adopting this structure, we can take advantage of task-level pipelines on the FPGA side, effectively utilizing time and space resources. Secondly, we utilize LDL decomposition to perform the inversion of the Hermitian matrix, which not only exhibits the lowest computational complexity and requires fewer computational resources but also achieves a higher level in the parallel pipeline mechanism compared with other alternative methods. Furthermore, the algorithm conducts iterations sequentially, utilizing the parameters derived from the previous dataset as prior information for initializing the subsequent dataset’s initial values. This approach helps to reduce the number of iterations required. Finally, with the help of Vitis HLS 2022.2 and Vivado tools, we successfully accomplished the development of a hardware design language and its implementation on the ZYNQ UltraScale+ MPSoC ZCU102 platform. Meanwhile, we have solved a direction of arrival (DOA) estimation problem using horizontal line arrays to verify the practical feasibility of the method.

Novel Techniques for Smart Adaptive Multiprocessor SoCs

The growing concerns of power efficiency, silicon reliability and performance scalability motivate research in the area of adaptive embedded systems, i.e. systems endowed with decisional capacity, capable of online decision making so as to meet certain performance criteria. The scope of possible adaptation strategies is subject to the targeted architecture specifics, and may range from simple scenario-driven frequency/voltage scaling to rather complex heuristic-driven algorithm selection. This paper advocates the design of distributed memory homogeneous multiprocessor systems as a suitable template for best exploiting adaptation features, thereby tackling the aforementioned challenges. The proposed solution lies in the combined use of a typical application processor for global orchestration along with such an adaptive multiprocessor core for the handling of data-intensive computation. This paper describes an exploratory homogeneous multiprocessor template designed from the ground up for scalability and adaptation. The proposed contributions aim at increasing architecture efficiency through smart distributed control of architectural parameters such as frequency, and enhanced techniques for load balancing such as task migration and dynamic multithreading.

Design Space Exploration of DVFS on On-Chip Hybrid Communication Networks

Multi-Processor Systems-on-Chip (MPSoCs) have been established as the standard platform for high-performance applications in the semiconductor industry. With an increasing number of Processing Elements (PEs) in a single die, communication scalability is one of the foremost concerns. Networks-on-Chip (NoCs) has already shown to be an alternative to provide scalability, but relies on homogeneous communication fashion which cannot be ideal to heterogeneous communication demand of current embedded devices. Hybrid communication structures can mitigate such issues by merging different communication structures that can better accommodate heterogeneous communication rates. In this work, an Hybrid Communication Infrastructure is proposed by merging fully- partially- and peer to peer connected fabrics providing a wide range of communication bandwidth. In addition, we coupled to the hybrid fabric, a multi-grained DVFS approach that dynamically adapts voltage and frequency of the structures considering the application's performance needs. Results shows that the Hybrid structure achieves up to 22% power savings and occupied 42% less chip area than a NoC with the same number of PEs. Experiments with relevant video encoding applications show power savings of up to 70% over a homogeneous NoC, with no significant throughput losses, both coupled to the proposed DVFS approach.

Mapping of Deep Neural Network Accelerators on Wireless Multistage Interconnection NoCs

In the last few decades, the concept of Wireless Network-on-chip (WiNoC) has emerged as a promising alternative for Multiprocessor Systems on Chip (MPSOC) to achieve reliable and scalable communication. Worth recalling in this regard is that our research team has already designed, verified and evaluated Multistage Interconnection Networks (MIN) in this field. With respect to the present work, we consider proceeding with further exploring our thoughts on this research area. Firstly, we propose the design and performance evaluation of a hybrid (wireless/wired) MIN, analysing how this augmented network can potentially improve not only the average delay, but also energy consumption. Secondly, we continue with examining the implementation of our advanced DELTA-based MIN architecture on Deep Neural Network (DNN) accelerators, while accounting for its potential regularity and scalability in simultaneously maintaining an effective power efficiency and lower latency throughout the DNN operating process. In this context, several metrics have been evaluated in regard to three DNN application cases through implementation of their main respective modules.

Enhancement of Deep Neural Network Recognition on MPSoC with Single Event Upset.

This paper introduces a new finding regarding single event upsets (SEUs) in configuration memory, and their potential impact on enhancing the performance of deep neural networks (DNNs) on the multiprocessor system on chip (MPSoC) platform. Traditionally, SEUs are considered to have negative effects on electronic systems or designs, but the current study demonstrates that they can also have positive contributions to the DNN on the MPSoC. The assertion that SEUs can have positive contributions to electronic system design was supported by conducting fault injections through dynamic reconfiguration on DNNs implemented on a 16nm FinFET technology Zynq UltraScale+ MPSoC. The results of the current study were highly significant, indicating that an SEU in configuration memory could result in an impressive 8.72% enhancement in DNN recognition on the MPSoC. One possible cause is that SEU in the configuration memory leads to slight changes in weight or bias values, resulting in improved activation levels of neurons and enhanced final recognition accuracy. This discovery offers a flexible and effective solution for boosting DNN performance on the MPSoC platform.

FPGA-Based CNN for Eye Detection in an Iris Recognition at a Distance System

Neural networks are the state-of-the-art solution to image-processing tasks. Some of these neural networks are relatively simple, but the popular convolutional neural networks (CNNs) can consist of hundreds of layers. Unfortunately, the excellent recognition accuracy of CNNs comes at the cost of very high computational complexity, and one of the current challenges is managing the power, delay and physical size limitations of hardware solutions dedicated to accelerating their inference process. In this paper, we describe the embedding of an eye detection system on a Zynq XCZU4EV UltraScale+ multiprocessor system-on-chip (MPSoC). This eye detector is used in the application framework of a remote iris recognition system, which requires high resolution images captured at high speed as input. Given the high rate of eye regions detected per second, it is also important that the detector only provides as output images eyes that are in focus, discarding all those seriously affected by defocus blur. In this proposal, the network will be trained only with correctly focused eye images to assess whether it can differentiate this pattern from that associated with the out-of-focus eye image. Exploiting the neural network’s advantage of being able to work with multi-channel input, the inputs to the CNN will be the grey level image and a high-pass filtered version, typically used to determine whether the iris is in focus or not. The complete system synthetises other cores and implements CNN using the so-called Deep Learning Processor Unit (DPU), the intellectual property (IP) block released by AMD/Xilinx. Compared to previous hardware designs for implementing FPGA-based CNNs, the DPU IP supports extensive deep learning core functions, and developers can leverage DPUs to conveniently accelerate CNN inference. Experimental validation has been successfully addressed in a real-world scenario working with walking subjects, demonstrating that it is possible to detect only eye images that are in focus. This prototype module includes a CMOS digital image sensor that provides 16 Mpixel images, and outputs a stream of detected eyes as 640 × 480 images. The module correctly discards up to 95% of the eyes present in the input images as not being correctly focused.

MaGNAS: A Mapping-Aware Graph Neural Architecture Search Framework for Heterogeneous MPSoC Deployment

Graph Neural Networks (GNNs) are becoming increasingly popular for vision-based applications due to their intrinsic capacity in modeling structural and contextual relations between various parts of an image frame. On another front, the rising popularity of deep vision-based applications at the edge has been facilitated by the recent advancements in heterogeneous multi-processor Systems on Chips (MPSoCs) that enable inference under real-time, stringent execution requirements. By extension, GNNs employed for vision-based applications must adhere to the same execution requirements. Yet contrary to typical deep neural networks, the irregular flow of graph learning operations poses a challenge to running GNNs on such heterogeneous MPSoC platforms. In this paper, we propose a novel unified design-mapping approach for efficient processing of vision GNN workloads on heterogeneous MPSoC platforms. Particularly, we develop MaGNAS, a mapping-aware Graph Neural Architecture Search framework. MaGNAS proposes a GNN architectural design space coupled with prospective mapping options on a heterogeneous SoC to identify model architectures that maximize on-device resource efficiency. To achieve this, MaGNAS employs a two-tier evolutionary search to identify optimal GNNs and mapping pairings that yield the best performance trade-offs. Through designing a supernet derived from the recent Vision GNN (ViG) architecture, we conducted experiments on four (04) state-of-the-art vision datasets using both ( i ) a real hardware SoC platform (NVIDIA Xavier AGX) and ( ii ) a performance/cost model simulator for DNN accelerators. Our experimental results demonstrate that MaGNAS is able to provide 1.57 × latency speedup and is 3.38 × more energy-efficient for several vision datasets executed on the Xavier MPSoC vs. the GPU-only deployment while sustaining an average 0.11% accuracy reduction from the baseline.

Design and Implementation of High QoS 3D-NoC using Modified Double Particle Swarm Optimization on FPGA

One technique to overcome the exponential growth bottleneck is to increase the number of cores on a processor, although having too many cores might cause issues including chip overheating and communication blockage. The problem of the communication bottleneck on the chip is presently effectively resolved by networks-on-chip (NoC). A 3D stack of chips is now possible, thanks to recent developments in IC manufacturing techniques, enabling to reduce of chip area while increasing chip throughput and reducing power consumption. The automated process associated with mapping applications to form three-dimensional NoC architectures is a significant new path in 3D NoC research. This work proposes a 3D NoC partitioning approach that can identify the 3D NoC region that has to be mapped. A double particle swarm optimization (DPSO) inspired algorithmic technique, which may combine the characteristics having neighbourhood search and genetic architectures, also addresses the challenge of a particle swarm algorithm descending into local optimal solutions. Experimental evidence supports the claim that this hybrid optimization algorithm based on Double Particle Swarm Optimisation outperforms the conventional heuristic technique in terms of output rate and loss in energy. The findings demonstrate that in a network of the same size, the newly introduced router delivers the lowest loss on the longest path. Three factors, namely energy, latency or delay, and throughput, are compared between the suggested 3D mesh ONoC and its 2D version. When comparing power consumption between 3D ONoC and its electronic and 2D equivalents, which both have 512 IP cores, it may save roughly 79.9% of the energy used by the electronic counterpart and 24.3% of the energy used by the latter. The network efficiency of the 3D mesh ONoC is simulated by DPSO in a variety of configurations. The outcomes also demonstrate an increase in performance over the 2D ONoC. As a flexible communication solution, Network-On-Chips (NoCs) have been frequently employed in the development of multiprocessor system-on-chips (MPSoCs). By outsourcing their communication activities, NoCs permit on-chip Intellectual Property (IP) cores to communicate with one another and function at a better level. The important components in assigning application duties, distributing the work to the IPs, and coordinating communication among them are mapping and scheduling methods. This study aims to present an entirely advanced form of research in the area of 3D NoC mapping and scheduling applications, grouping the results according to various parameters and offering several suggestions for further research.

Real-Time Embedded Eye Image Defocus Estimation for Iris Biometrics.

One of the main challenges faced by iris recognition systems is to be able to work with people in motion, where the sensor is at an increasing distance (more than 1 m) from the person. The ultimate goal is to make the system less and less intrusive and require less cooperation from the person. When this scenario is implemented using a single static sensor, it will be necessary for the sensor to have a wide field of view and for the system to process a large number of frames per second (fps). In such a scenario, many of the captured eye images will not have adequate quality (contrast or resolution). This paper describes the implementation in an MPSoC (multiprocessor system-on-chip) of an eye image detection system that integrates, in the programmable logic (PL) part, a functional block to evaluate the level of defocus blur of the captured images. In this way, the system will be able to discard images that do not have the required focus quality in the subsequent processing steps. The proposals were successfully designed using Vitis High Level Synthesis (VHLS) and integrated into an eye detection framework capable of processing over 57 fps working with a 16 Mpixel sensor. Using, for validation, an extended version of the CASIA-Iris-distance V4 database, the experimental evaluation shows that the proposed framework is able to successfully discard unfocused eye images. But what is more relevant is that, in a real implementation, this proposal allows discarding up to 97% of out-of-focus eye images, which will not have to be processed by the segmentation and normalised iris pattern extraction blocks.

Design and Develop Efficient Arbitration Technique to Handle the Multiple Refresh Requests in Multi-Processor SoC

Emerging memory technologies, such as Gain Cell-embedded Dynamic Random Access Memory (GC-eDRAM), play an essential part in the process of improving the overall performance of current multi-processor systems. GC-eDRAM, on the other hand, has its own set of distinct issues, particularly with regard to refresh operations. The number of cores and threads in contemporary processors continues to expand, which in turn leads to an increase in the number of concurrent refresh requests. This might cause contention, which in turn can lead to a possible performance decrease. In this article, we present an efficient arbitration method that was developed in order to precisely address the issues that are associated with numerous requests for a refresh in GC-eDRAM. This method takes use of the inherent parallelism of GC-eDRAM modules to make it possible to execute simultaneous refresh operations. As a result, contention is effectively reduced, and the overall performance of the system is improved. We provide a new arbitration method that prioritizes the pending refresh requests according to their level of urgency and optimizes the allocation of GC-eDRAM resources in order to guarantee that refresh operations are carried out in an effective manner. Our method modifies the arbitration priority in a dynamic manner according to the characteristics of the active workload. These characteristics include the request arrival rate, memory access patterns, and data location, among other considerations.