Evaluation and validation of efficient hierarchical interconnection in multi-processor system on chip

Abstract

ABSTRACT Multiprocessor system-on-chip (MPSoC) is increasingly used in today’s complicated embedded systems. This paper uses an efficient Hierarchical Interconnection Framework (EHIF) to improve throughput and latency over traditional 3D mesh NoC. The suggested router is hierarchical with one module handling inter-layer communication and intra-layer communication. The EHIF compares well to the traditional 3D mesh in terms of area and power consumption. The EHIF method reduced the execution time without increasing the memory buffer size to optimise time and memory. It achieves a high performance ratio, throughput, low power consumption, latency and delay compared to other methods