Multi-output Boolean Functions Research Articles

RECURSIVE TERNARY-BASED ALGORITHM FOR COMPUTING PRIME IMPLICANTS OF MULTI-OUTPUT BOOLEAN FUNCTIONS

The problem of computing the set of prime implicants to represent a Boolean function is a classical problem that is still considered a running problem for research because all known approaches have limitations. The article reviews existing methods for computing prime implicants and highlights their limitations, particularly for multi-output functions and limited scalability due to the growth in memory required to complete the computation. Then it proposes a recursive ternary-based minimization algorithm to compute the prime implicants of multi-output Boolean functions. The algorithm is based on the concept of Programmable Logic Array (PLA) tables, which provide a structured and efficient representation of Boolean functions. The algorithm takes advantage of the ternary logic system to efficiently compute the prime implicants while maintaining scalability for large and complex functions, which has significant implications for digital circuit design and optimization.

A new method for logic optimization of QCA-based circuits using a golden ball algorithm

Quantum-dot Cellular Automata (QCA) is an approach for constructing low-power digital circuits and various high-performance calculations at the nano-scale. This technique has little power dissipation due to its nature. Implementing circuits using QCA is an active research topic because of the necessary qualities, like short switching time, high device density, and comparatively low power. The primary gates in this technology are the inverter and majority gates, which can function as universal logic gates to build any circuit. This study provides an effective approach to synthesize multi-output Boolean functions using QCA circuits. Due to the NP-hard nature of the logic optimization problem, a golden ball algorithm-based method is utilized to decrease delay time and energy usage in the design process. The simulations utilizing MATLAB software are used to test the functionality of the suggested approach. The empirical findings indicate that the suggested technique performs better than prior methods in numerous instances.

BDD-Based Error Metric Analysis, Computation and Optimization

Approximate Computing is a design paradigm that trades off computational accuracy for gains in non-functional aspects such as reduced area, increased computation speed, or power reduction. Computing the error of the approximated design is an essential step to determine its quality. The computation time for determining the error can become very large, effectively rendering the entire logic approximation procedure infeasible. In this work we extensively analyze various error metrics and approximation operations. We present methods to accelerate the computation of error metric computations by 1) exploiting structural information of the function obtained by applying the analyzed operations and 2) computing estimates of the metrics for multi-output Boolean functions represented as Binary Decision Diagrams (BDDs). We further present a novel greedy, bucket-based BDD minimization framework employing the newly proposed error metric computations to produce Pareto-optimal solutions with respect to BDD size and multiple error metrics. The applicability of the proposed minimization framework is demonstrated by an experimental evaluation. We can report considerable speedups while, at the same time, creating high-quality approximated BDDs. The presented framework is publicly available as open-source software on GitHub.

Quantum Algorithms for the Resiliency of Vectorial Boolean Functions

Recently, Cui and Guo (Quantum Inform. Process. 18, 182, 2019) gave some quantum testing algorithms of multi-output Boolean functions, one of them was for resiliency testing. However, through the algorithm, we cannot get the probability distribution of a Boolean function. Improving the algorithm there, we present quantum algorithms for this problem. Under the condition of non-resiliency, we obtain not only the conclusion that the function F(x) is statistically dependent of which t variables but also the distance of the probability distribution from the uniform distribution.

New characterizations for the multi-output correlation-immune Boolean functions

Correlation-immune (CI) multi-output Boolean functions have the property of keeping the same output distributions when some input variables are fixed. Recently, a new application of CI functions has appeared in the system of resisting side-channel attacks (SCA). In this paper, three new methods are proposed to characterize the tth-order CI multi-output (n-input and m-output) Boolean functions. The first characterization is to regard the multi-output Boolean functions as the corresponding generalized Boolean functions. It is shown that a generalized Boolean function fg is a tth-order CI function if and only if the Walsh transform of fg defined here vanishes at all points with Hamming weights between 1 and t. The last two methods are generalized from Fourier spectral characterizations. Especially, Fourier spectral characterizations are efficient to characterize the symmetric multi-output CI Boolean functions.

Quantum cryptographic property testing of multi-output Boolean functions

Compared with Boolean functions, multi-output Boolean functions (a.k.a. vectorial Boolean functions) are commonly used in classical cryptography. More generally, many cryptographic primitives can be treated as multi-output Boolean functions. Hence, the research on property testing of multi-output Boolean functions is meaningful for the design and cryptanalysis of symmetric cryptography. This paper mainly focuses on the cryptographic property testing of multi-output Boolean functions in the quantum world. Firstly, the generalized Deutsch–Jozsa algorithm is proposed to distinguish balanced multi-output Boolean functions from constant ones with a single query. This algorithm has a wider scope of applications with arbitrary ancillary inputs. The first generalized Bernstein–Vazirani algorithm suitable for multi-output Boolean functions is presented to recover the linear coefficients of linear functions. Then, combined with the generalized Deutsch–Jozsa algorithm, the quantum algorithm for estimating Walsh coefficients of multi-output Boolean functions is proposed with the same idea of quantum approximate counting algorithm, accompanied with an algorithm for computing the Walsh coefficient at a specified point based on quantum exact counting algorithm. Finally, with the usage of algorithms mentioned above, the cryptographic property testing of multi-output Boolean functions is studied. In order to describe the distances from having the certain properties, Euclidean distance and Manhattan distance are introduced as complements of Hamming distance. According to the definition, the first balance testing of multi-output Boolean functions is presented by testing the uniformity of images. The second algorithm exploits the relationship between balance and the Walsh coefficients at the point 0 which could be easily extended to k-order resiliency testing. We also briefly analyze the query complexities of strict avalanche criterion testing and k-order propagation criteria testing. The linearity testing algorithm for multi-output Boolean functions based on the generalized Bernstein–Vazirani algorithm can be adapted to Boolean functions achieving a further speedup. The non-junta testing algorithm is proposed with lower query complexity.

Quantum algorithms for learning Walsh spectra of multi-output Boolean functions

In classical cryptography, many cryptographic primitives could be treated as multi-output Boolean functions. The analysis of such functions is of great interest for cryptologists owing to their wide ranges of applications. Since each multi-output Boolean function can be uniquely determined by its Walsh transform, the Walsh spectra could reveal the properties of multi-output Boolean functions. In this paper, several quantum algorithms for learning Walsh spectra of multi-output Boolean functions are proposed. Firstly, with the usage of the amplitude estimation algorithm based on the Monte Carlo method, we present a quantum algorithm that allows one to estimate the Walsh coefficient of a multi-output Boolean function at a specified point with an additive error \(\epsilon \) and probability at least \(1-\delta \). The corresponding query complexity is \({\mathrm O}( {{\epsilon }^{-1}}\log {{\delta }^{-1}} )\). There is an almost quadratic speedup over the classical algorithm. Secondly, we propose a generalized phase kick-back technique for multi-output Boolean functions to encode multiple Walsh coefficients on the amplitudes of states. Based on this generalized technique, a quantum Goldreich–Levin algorithm for arbitrary multi-output Boolean function \(F:{{\{ 0,1 \}}^{n}}\rightarrow {{\{ 0,1 \}}^{m}}\) where \(m,n\in \mathbb {Z}\) is proposed to find those Walsh coefficients satisfying the threshold boundary condition \(\tau \) with probability at least \(1-\delta \). The whole query complexity is \({\mathrm O}\left( \frac{{{2}^{m+5+n/2}}}{{{\tau }^{3}}}\log \frac{{{2}^{m+5}}n}{\delta {{\tau }^{2}}} \right) \). Finally, by using the same idea of the swap-test circuit, the query complexity of the modified quantum Goldreich–Levin algorithm could be lowered to \({\mathrm O}\left( \frac{{{2}^{m+9}}n\pi }{{{\tau }^{4}}}\log \frac{{{2}^{m+3}}n}{\delta {{\tau }^{2}}} \right) \) achieving a further speedup when \(\tau \) is no less than \({\mathrm O}( {{2}^{-n/2+6}}n)\). Those two quantum Goldreich–Levin algorithms have their own advantages in implementation and query complexity.

Efficient Mapping of Boolean Functions to Memristor Crossbar Using MAGIC NOR Gates

Memristor is considered as a promising circuit element which can be used in many applications. Various synthesis methods for Boolean functions have been explored in the literature using memristor-based design styles. Memristor crossbar is considered as one of the most preferred structures for implementing logic functions as well as memory. In this paper, a general synthesis flow has been proposed using the MAGIC logic design style to map multioutput Boolean functions to memristor crossbars. The functions are realized as a netlist of NOR and NOT gates. Two alternate methods of evaluating the gates are used, serial and parallel, which give a tradeoff between the number of cycles and the size of the crossbar. A strategy for scheduling the gates to time steps has also been proposed to reduce the hardware overhead. The switching delays and energy requirements are estimated using SPICE simulation. Synthesis results are reported for ISCAS’85 benchmark functions that show an average reduction of 68.8% in the number of cycles, 52.8% in energy consumption, and 96.4% in the number of memristors required as compared to a very recently published work.

A Comparative Study of Majority/Minority Logic Circuit Synthesis Methods for Post-CMOS Nanotechnologies

The physical limitations of complementary metal-oxide semiconductor (CMOS) technology have led many researchers to consider other alternative technologies. Quantum-dot cellular automate (QCA), single electron tunneling (SET), tunneling phase logic (TPL), spintronic devices, etc., are some of the nanotechnologies that are being considered as possible replacements for CMOS. In these nanotechnologies, the basic logic units used to implement circuits are majority and/or minority gates. Several majority/minority logic circuit synthesis methods have been proposed. In this paper, we give a comparative study of the existing majority/minority logic circuit synthesis methods that are capable of synthesizing multi-input multi-output Boolean functions. Each of these methods is discussed in detail. The optimization priorities given to different factors such as gates, levels, inverters, etc., vary with technologies. Based on these optimization factors, the results obtained from different synthesis methods are compared. The paper also analyzes the optimization capabilities of different methods and discusses directions for future research in the synthesis of majority/minority logic networks.

A multi-objective synthesis methodology for majority/minority logic networks

New technologies such as quantum-dot cellular automata, single-electron tunneling, tunneling phase logic, and all-spin logic devices have been widely advocated in nanotechnology as a response to the physical limits associated with complementary metal---oxide---semiconductor technology at atomic scales. Some of their peculiar features are their smaller size, higher speed, higher switching frequency, lower power consumption, and higher scale integration. In these technologies, the majority (or minority) and inverter gates are employed for the production of the functions as this set of gates makes a universal set of Boolean primitives in these technologies. An important step in the generation of Boolean functions using the majority gate is reducing the number of involved gates. In this paper, a multi-objective synthesis methodology (with the objective priority of gate counts, gate levels, and the number of inverter gates) is presented for finding the minimal number of possible majority gates in the synthesis of Boolean functions using the proposed majority specification matrix (MSM) concept. Moreover, based on MSM, a synthesis flow is proposed for the synthesis of multi-output Boolean functions. To reveal the efficiency of the proposed method, it is compared with a meta-heuristic method, multi-objective genetic programing (GP). Besides, it is applied to synthesize MCNC benchmark circuits. The results are indicative of the outperformance of the proposed method in comparison to the multi-objective GP method. Also, for the MCNC benchmark circuits, there is an average reduction of 10.5% in the number of levels as well as 16.8% and 33.5% in the number of majority and inverter gates, respectively, as compared to the best available method.

Memristor-Based Volistor Gates Compute Logic with Low Power Consumption

We introduce a novel volistor logic gate which uses voltage as input and resistance as output. Volistors rely on the diode-like behavior of rectifying memristors. We show how to realize the first logic level, counted from the input, of any Boolean function with volistor gates in a memristive crossbar network. Unlike stateful logic, there is no need to store the inputs as resistances, and computation is performed directly. The fan-in and fan-out of volistor gates are large and different from traditional memristor circuits. Compared to solely memristive stateful logic, a combination of volistors and stateful inhibition gates can significantly reduce the number of operations required to calculate arbitrary multi-output Boolean functions. The power consumption of volistor logic is computed and compared with the power consumption of stateful logic using the simulation results obtained by LTspice—when implemented in a 1 × 8 or an 8 × 1 crosspoint array, volistors consume significantly less power.

Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits

The increased number of complex functional units exerts high power-density within a very-large-scale integration (VLSI) chip which results in overheating. Power-densities directly converge into temperature which reduces the yield of the circuit. An adverse effect of power-density reduction is the increase in area. So, there is a trade-off between area and power-density. In this paper, we introduce a Shared Reed-Muller Decision Diagram (SRMDD) based on fixed polarity AND-XOR decomposition to represent multioutput Boolean functions. By recursively applying transformations and reductions, we obtained a compact SRMDD. A heuristic based on Genetic Algorithm (GA) increases the sharing of product terms by judicious choice of polarity of input variables in SRMDD expansion and a suitable area and power-density trade-off has been enumerated. This is the first effort ever to incorporate the power-density as a measure of temperature estimation in AND-XOR expansion process. The results of logic synthesis are incorporated with physical design in CADENCE digital synthesis tool to obtain the floor-plan silicon area and power profile. The proposed thermal-aware synthesis has been validated by obtaining absolute temperature of the synthesized circuits using HotSpot tool. We have experimented with 29 benchmark circuits. The minimized AND-XOR circuit realization shows average savings up to 15.23% improvement in silicon area and up to 17.02% improvement in temperature over the sum-of-product (SOP) based logic minimization.

On the nonlinearity of S-boxes and linear codes

For multi-output Boolean functions (also called S-boxes), various measures of nonlinearity have been widely discussed in the literature but many problems are left open in this topic. The purpose of this paper is to present a new approach to estimating the nonlinearity of S-boxes. A more fine-grained view on the notion of nonlinearity of S-boxes is presented and new connections to some linear codes are established. More precisely, we mainly study the nonlinearity indicator (denoted by ??v$\mathcal {N}_{\mathrm {v}}$) for S-boxes from a coding theory point of view. Such a cryptographic parameter ??v$\mathcal {N}_{\mathrm {v}}$ is more related to best affine approximation attacks on stream ciphers. We establish a direct link between ??v$\mathcal {N}_{\mathrm {v}}$ and the minimum distance of the corresponding linear code. We exploit that connection to derive the first general lower bounds on ??v$\mathcal {N}_{\mathrm {v}}$ of non-affine functions from ??2n$\mathbb {F}_{2^{n}}$ to ??2m$\mathbb {F}_{2^{m}}$ for m dividing n. Furthermore, we show that ??v$\mathcal {N}_{\mathrm {v}}$ can be determined directly by the weight distribution of the corresponding linear code.

Walsh Spectral Techniques for Logic Synthesis FPGA

The implementation value of multi-output Boolean functions in logic synthesis FPGA can be reduced by using Walsh spectral representation. This paper proposes an algorithm for calculating the maximum coefficient of the autocorrelation function of BF without generating a truth table, using the heuristic procedure limits the maximum autocorrelation coefficients of sorting on a small subset of the function. We also suggest a spectral technique of the linear function transformation defined by disjoint cubes. This method for decomposition of BF, which allows to reducing the complexity of the linear part of the corresponding blocks about 25-55%, and the complexity of the nonlinear part of the blocks do not increase more than 10%, compared to the traditional approach.

Bent vectorial functions and linear codes from o-polynomials

The main topics and interconnections arising in this paper are symmetric cryptography (S-boxes), coding theory (linear codes) and finite projective geometry (hyperovals). The paper describes connections between the two main areas of information theory on the one side and finite geometry on the other side. Bent vectorial functions are maximally nonlinear multi-output Boolean functions. They contribute to an optimal resistance to both linear and differential attacks of those symmetric cryptosystems in which they are involved as substitution boxes (S-boxes). We firstly exhibit new connections between bent vectorial functions and the hyperovals of the projective plane, extending the recent link between bent Boolean functions and the hyperovals. Such a link provides several new classes of optimal vectorial bent functions. Secondly, we exhibit surprisingly a connection between the hyperovals of the projective plane in even characteristic and $$q$$q-ary simplex codes. To this end, we present a general construction of classes of linear codes from o-polynomials and study their weight distribution proving that all of them are constant weight codes. We show that the hyperovals of $$PG_{2}(2^m)$$PG2(2m) from finite projective geometry provide new minimal codes (used in particular in secret sharing schemes, to model the access structures) and give rise to multiples of $$2^r$$2r-ary ($$r$$r being a divisor of $$m$$m) simplex linear codes (whose duals are the perfect $$2^r$$2r-ary Hamming codes) over an extension field $${\mathbb F}_{2^{r}}$$F2r of $${\mathbb F}_{2^{}}$$F2. The following diagram gives an indication of the main topics and interconnections arising in this paper. [Figure not available: see fulltext.]

Asymptotic lower bound on the algebraic immunity of random balanced multi-output Boolean functions

This paper extends the work of F. Didier (IEEE Transactions on Information Theory, Vol. 52(10): 4496-4503, October 2006) on the algebraic immunity of random balanced Boolean functions, into an asymptotic lower bound on the algebraic immunity of random balanced multi-output Boolean functions.

On the construction of multi-output Boolean functions with optimal algebraic immunity

In this paper, we show a construction of multi-output Boolean functions with optimal algebraic immunity. And, the relationship between the algebraic immunity of a multi-output Boolean function and those of its component functions is studied. We show that all the component functions, together with their nonzero linear combination, of the multi-output Boolean functions achieved by this construction have optimal algebraic immunity simultaneously.

AND-OR-XOR NETWORK SYNTHESIS WITH AREA-POWER TRADE-OFF

In this paper, a heuristic based on genetic algorithm to realize multi-output Boolean function as three-level AND-OR-XOR network performing area power trade-off is presented. All the previous works dealt with the minimization of number of product terms only in the two sum-of-product-expressions representing a Boolean function during AND-OR-XOR network synthesis. To the best of knowledge this is the first ever effort to incorporate total power, that is, dynamic and leakage power along with the area (in terms of number of product terms) during three-level AND-OR-XOR networks synthesis. The synthesis process, without changing the delay performance results in lesser number of product terms compared to those reported in the literature. It also enumerates the trade-offs present in the solution space for different weights associated with area, dynamic power, and leakage power of the resulting circuit.

On the construction of bent vectorial functions

This paper is devoted to the constructions of bent vectorial functions, that is, maximally non-linear multi-output Boolean functions. Such functions contribute to an optimal resistance to both linear and differential attacks of those cryptosystems in which they are involved as substitution boxes (S-boxes). We survey, study more in details and generalise the known primary and secondary constructions of bent functions, and we introduce new ones.

A notion of r-admissibility and its application in logic synthesis

Abstract This paper presents a theory for disjoint and non-disjoint multi-output Boolean function decomposition. This method is dedicated for FPGAs with embedded memory blocks (EMB). Proposed technique is an extension of known approach commonly used for LUT-based FPGA structures. A scheme for generating the set of bound variables that make the function decomposable is presented. Experiments that were carried out show significant area reduction.