Walsh Spectral Techniques for Logic Synthesis FPGA

Nhan Khanh Huu Nguyen

doi:10.15598/aeee.v13i2.1117

Abstract

The implementation value of multi-output Boolean functions in logic synthesis FPGA can be reduced by using Walsh spectral representation. This paper proposes an algorithm for calculating the maximum coefficient of the autocorrelation function of BF without generating a truth table, using the heuristic procedure limits the maximum autocorrelation coefficients of sorting on a small subset of the function. We also suggest a spectral technique of the linear function transformation defined by disjoint cubes. This method for decomposition of BF, which allows to reducing the complexity of the linear part of the corresponding blocks about 25-55%, and the complexity of the nonlinear part of the blocks do not increase more than 10%, compared to the traditional approach.

Highlights

There are two popular categories of field programmable gate array (FPGA) block structures, namely LookUp Table-based (LUT) and multiplexor-based (MB); the resulting architectures are called LUT-based and MUX-based architectures respectively [1].The basic block of an LUT architecture is a look-up table that can implement any Boolean function of up to m inputs, m ≥ 2
Increasing complexity of both the integrated density and application requirements become higher every pasing day. Those are questions of design and development of algorithms for automatic logic synthesis. It follows that the main problems of logic synthesis in the FPGAs minimize the number of used logic blocks and reduce the complexity of the trace
We use the linearization procedure of BF, as described above: after deleting the coefficient B(0), we find that the maximum coefficient of the autocorrelation function of BF is 18 with the number of columns τ0 = 10, which corresponds to the binary representation of 1010

Summary

Introduction

There are two popular categories of field programmable gate array (FPGA) block structures, namely LookUp Table-based (LUT) and multiplexor-based (MB); the resulting architectures are called LUT-based and MUX-based architectures respectively [1]. The first generation of LCA devices appeared in 1985 They consist of logical blocks that include the generator combination of functions that implements the 4-input foundation, and the only element of memory and the trigger. The maximum "occupancy" of the crystal does not exceed 70–80 %, since the greater utilization of the crystal having trouble tracing To solve this problem, the fourth generation architecture of the crystals (series XC5200), submitted in 1996, was redesigned in the direction of greater "traceability" and the possibility of more "waste" of resources. XC5200 family has five structures, ranging in complexity from 2000 to 23000 gates with the system clock frequency of 50 MHz. As already mentioned in this paper, the main difference between the latest developments in the area of the LCA devices, will based on static memory technology is to improve the characteristics of the trace of the crystal. It follows that the main problems of logic synthesis in the FPGAs minimize the number of used logic blocks and reduce the complexity of the trace

Spectral and Correlation Analysis of Boolean Functions

Decomposition of the Boolean Function

Linearization Algorithm

Disjoint Cubes Performance Analysis

Numerical Results

Conclusion and Future Extension